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DATA SHEET MOS INTEGRATED CIRCUIT PD78C17, 78C18 8-BIT SINGLE-CHIP MICROCONTROLLER (WITH A/D CONVERTER) The PD78C18 is an 8-bit CMOS microcontroller which integrates 16-bit ALU, ROM, RAM, an A/D converter, a multi-function timer/event counter, and a general-purpose serial interface onto a single chip, and whose memory (ROM/RAM) is externally expandable up to 31 Kbytes. The PD78C18 can operate at low power consumption because of its CMOS architecure and is provided with a standby function that enables data retention with an even lower power consumption. The PD78C17 is the ROM-less version of the PD78C18. Its memory (ROM/RAM) is expandable externally up to 63 Kbytes. A detailed explanation of the functions is provided in the user's manual listed below. It should be read before starting design work. 87AD Series PD78C18 User's Manual: IEU-1314 FEATURES * * * * * * * * 159 types of instructions: 87AD series instruction set plus multiply/divide and 16-bit operation instructions Instruction cycle: 0.8 s (at 15-MHz operation) Internal ROM: 32768 x 8 bits (PD78C18 only) Internal RAM: 1024 x 8 bits Up to 64 Kbytes of memory (ROM/RAM) can be directly addressed. High-resolution 8-bit A/D converter: 8 analog inputs General-purpose serial interface: Asynchronous, synchronous, I/O interface modes Multi-function 16-bit timer/event counter * Two 8-bit timers * I/O lines Input/output ports : 28 (PD78C17), 40 (PD78C18) Edge detection inputs : 4 * 11 interrupt functions External : 3, Internal: 8 (Non-maskable: 1, Maskable: 10) * Zero-cross detection function: (2 inputs) * Standby function: HALT mode, hardware/software STOP mode * Mask option pull-up resistors can be incorporated into Ports A, B, and C. (PD78C18 only) ORDERING INFORMATION Part Number Package 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin plastic plastic plastic plastic plastic plastic shrink DIP (750 mils) QFP (14 x 20 mm) QUIP shrink DIP (750 mils) QFP (14 x 20 mm) QUIP PD78C17CW PD78C17GF-3BE PD78C17GQ-36 PD78C18CW-xxx PD78C18GF-xxx-3BE PD78C18GQ-xxx-36 The information in this document is subject to change without notice. Document No. IC-2789B (O.D.No. IC-8048B) Date Published June 1995 P Printed in Japan The mark 5 shows revised points. (c) 1995 1990 PD78C17,78C18 PIN CONFIGURATION (TOP VIEW) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0/TXD PC1/RXD PC2/SCK PC3/INT2 PC4/TO PC5/CI PC6/CO0 PC7/CO1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD STOP PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 ALE WR RD AVDD AVAREF AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 AVSS PD78C17CW, PD78C17GQ-36 PD78C18CW-xxx, PD78C18GQ-xxx-36 m NMI INT1 MODE1 RESET MODE0 X2 X1 VSS m 2 PD78C17,78C18 VAREF AVDD AN7 AN6 34 PD3 PD4 PD5 PD6 PD7 STOP VDD PA0 PA1 PA2 PA3 PA4 PA5 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 33 32 31 30 29 28 27 AN5 PD2 PD1 PD0 ALE PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 WR RD AN4 AN3 AN2 AN1 AN0 AVSS VSS X1 X2 MODE0 RESET MODE1 INT1 PD78C17GF-3BE PD78C18GF-xxx-3BE 26 25 24 23 22 21 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 20 19 PC3/INT2 PC4/TO PC6/CO0 PC7/CO1 PC2/SCK PC0/TXD PC1/RXD PC5/CI PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 NMI 3 OSC X2 PORT F MAIN G.R 10 PROGRAMNote 1 MEMORY (32-KBYTE) 16 8 PORT D PORT C 8 PC5/CI PC6/CO0 PC7/CO1 TIMER/EVENT COUNTER 16 8 LATCH 16 LATCH INTERNAL DATA BUS 6 PSW 8 INST.REG 8 PORT B AN7-0 VAREF AVDD AVSS 8 A/D CONVERTER 8 16 16 8 ALU (8/16) INST. DECODER PORT A 4 X1 16 LATCH INC/DEC PC SP EA V B D H 8 INT1 INT. CONTROL 4 EA' V' B' D' H' BUFFER PC3/INT2/TI TIMER PC4/TO 8 8 8 PB7-0Note 3 8/16 A' C' E' L' ALT G.R A C E L 8 8 8 15 8 PF7-0/ AB15-8Note 2 PC0/TXD PC1/RXD PC2/SCK SERIAL I/O 8 8 PD7-0/ AD7-0Note 2 NMI DATANote 4 MEMORY (1-KBYTE) 8 8 PC7-0Note 3 8 PA7-0Note 3 16 BLOCK DIAGRAM Notes 1. 2. 3. 4. Program memory is not incorporated in the PD78C17. PF3 to PF0 and PD7 to PD0 are operated only as AB11 to AB8 and AD7 to AD0 in the PD78C17. Pull-up resistor can be incorporated by the mask option in the PD78C18. Can be used only when RAE bit of MM register is 1. When it is 0, an external memory is necessary. READ/WRITE CONTROL SYSTEM CONTROL STAND BY CONTROL PD78C17,78C18 RD WR ALE MODE1 MODE0 RESET STOP VDD VSS PD78C17,78C18 CONTENTS 1. PIN FUNCTIONS ..........................................................................................................................................7 1.1 1.2 1.3 1.4 LIST OF PIN FUNCTION ......................................................................................................................................7 PIN INPUT/OUTPUT CIRCUITS ..........................................................................................................................9 PIN MASK OPTIONS .........................................................................................................................................15 UNUSED PIN CONNECTIONS ..........................................................................................................................15 2. INTERNAL BLOCK FUNCTIONS ..............................................................................................................16 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 REGISTERS .........................................................................................................................................................16 ARITHMETIC LOGIC UNIT (ALU) .....................................................................................................................17 PROGRAM STATUS WORD (PSW) ..................................................................................................................17 MEMORY ............................................................................................................................................................19 PORT FUNCTIONS .............................................................................................................................................22 TIMER ..................................................................................................................................................................31 TIMER/EVENT COUNTER .................................................................................................................................34 SERIAL INTERFACE ...........................................................................................................................................41 2.9 ANALOG/DIGITAL CONVERTER ......................................................................................................................52 2.10 ZERO-CROSS DETECTOR .................................................................................................................................55 3. INTERRUPT FUNCTIONS .........................................................................................................................57 3.1 3.2 3.3 3.4 INTERRUPT CONTROL CIRCUIT CONFIGURATION ......................................................................................58 NON-MASKABLE INTERRUPT OPERATION ...................................................................................................61 MASKABLE INTERRUPT OPERATION ............................................................................................................63 INTERRUPT OPERATION BY SOFTI INSTRUCTION ......................................................................................64 4. STANDBY FUNCTIONS ............................................................................................................................65 4.1 4.2 4.3 4.4 4.5 4.6 4.7 HALT MODE .......................................................................................................................................................65 HALT MODE RELEASE ......................................................................................................................................66 SOFTWARE STOP MODE .................................................................................................................................68 SOFTWARE STOP MODE RELEASE ................................................................................................................68 HARDWARE STOP MODE .................................................................................................................................69 HARDWARE STOP MODE RELEASE ...............................................................................................................70 LOW SUPPLY VOLTAGE DATA RETENTION MODE ..................................................................................... 71 5. 6. RESET OPERATIONS ................................................................................................................................72 INSTRUCTION SET ...................................................................................................................................73 6.1 6.2 6.3 IDENTIFIER/DESCRIPTION OF OPERAND ......................................................................................................73 SYMBOL DESCRIPTION OF INSTRUCTION CODE ........................................................................................74 INSTRUCTION EXECUTION TIME ...................................................................................................................75 7. 8. 9. LIST OF MODE REGISTERS .....................................................................................................................87 ELECTRICAL SPECIFICATIONS ................................................................................................................88 CHARACTERISTIC CURVES .....................................................................................................................99 10. PACKAGE DRAWINGS ...........................................................................................................................102 5 PD78C17,78C18 11. RECOMMENDED SOLDERING CONDITIONS ......................................................................................105 12. DIFFERENCES AMONG PD78C18, PD78C14, AND PD78C12A ....................................................106 APPENDIX. DEVELOPMENT TOOLS ..........................................................................................................107 6 PD78C17,78C18 1. PIN FUNCTIONS 1.1 LIST OF PIN FUNCTION (1/2) Pin Name PA7 to PA0 (Port A) PB7 to PB0 (Port B) PC0/TXD I/O Input-output Function 8-bit input-output port, which can specify input/output (Port A) bit-wise. 8-bit input-output port, which can specify input/output (Port B) bit-wise. Input-output Input-output/ Output Input-output/ Input Input-output/ Input-output Port C 8-bit input-output port, which can specify input/output bit-wise. Transmit Data Output pin for serial data. Receive Data Input pin for serial data. Serial Clock Input-output pin for serial clock. It becomes output pin for the internal clock use, and input pin for the external. Interrupt Request/Timer Input Maskable interrupt input pin of the edge trigger (falling edge), or an external clock input pin for a timer. Also, it can be used as a zero-cross detection pin for AC input. Timer Output Square wave defining one cycle of internal clock or timer counter time as half cycle is output. Counter Input External pulse input pin to timer/event counter. Counter Output 0, 1 Programmable square wave output by timer/event counter. PC1/RxD PC2/SCK PC3/INT2/TI Input-output/ Input/Input PC4/TO Input-output/ Output PC5/CI Input-output/ Input Input-output/ Output PC6/CO0 PC7/CO1 PD7 to PD0/ AD7 to AD0 PF7 to PF0/ AB15 to AB8 WR (Write Strobe) Input-output/ Input-output Input-output/ Output Output Port D 8-bit input-output port, which can specify input/output in byte units (PD78C18). Port F 8-bit input-output port, which can specify input/output bit-wise. Address/Data Bus When external memory is used, it becomes multiplexed address/data bus. Address Bus When external memory is used, it becomes address bus. Strobe signal which is output for write operation of external memory. It becomes high in any cycle other than the data write machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output highimpedance. Strobe signal which is output for read operation of external memory. It becomes high in any cycle other than the read machine cycle of external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. Strobe signal to latch externally the lower address information which is output to PD7 to PD0 pins to access external memory. When RESET signal is either low or in the hardware STOP mode, this signal becomes output high-impedance. RD (Read Strobe) Output ALE (Address Latch Enable) Output 7 PD78C17,78C18 1.1 LIST OF PIN FUNCTION (2/2) Pin Name MODE0 MODE1 (Mode) I/O Input-output Function The PD78C18 sets MODE0 pin to "0" (low level), and MODE1 pin to "1" (high level).Note The PD78C17 allows you to set MODE0, MODE1 pins to select 4 K, 16 K, or 63 Kbytes for the size of the memory which is installed externally. MODE0 0 1 1 MODE1 0 0 1 External Memory 4 Kbytes 16 Kbytes 63 Kbytes Also, when each of MODE0 and MODE1 pins is set to "1"Note, it is synchronized to ALE to output a control signal. NMI (Non-Maskable Interrupt) INT1 (Interrupt Request) AN7 to AN0 (Analog Input) VAREF (Reference Voltage) AVDD (Analog VDD) AVSS (Analog VSS) X1, X2 (Crystal) RESET (Reset) STOP (Stop) VDD VSS Input Input Non-maskable interrupt input pin of the edge trigger (falling edge) Input A maskable interrupt input pin of the edge trigger (rising edge). Also, it can be used as a zero-cross detection pin for AC input. 8 pins of analog input to A/D converter. AN7 to AN4 can be used as edge detection (falling edge) input. A common pin serving both as a reference voltage input pin for A/D converter and as a control pin for A/D converter operation. Input Input Power supply pin for A/D converter. GND pin for A/D converter. Crystal connection pins for system clock oscillation. X1 should be input when a clock is supplied from outside. Inverted clock of X1 should be input to X2. Low-level active system reset input. Input Control signal input pin in hardware STOP mode. The oscillation stops when the lowlevel is input. Positive power supply pin. GND pin. Note Remark Connect a pull-up resistor. Resistance R should be 4 [k] R 0.4tCYC [k] (tCYC is in nanoseconds). The PD78C18 can incorporate (mask option) pull-up resistors on to ports A, B, and C. 8 PD78C17,78C18 1.2 PIN INPUT/OUTPUT CIRCUITS Table 1-1 and 1-2, and figures (1) to (15) show input/output circuits of each pin in a schematic form. Table 1-1 Pin Type No. for PD78C17 Pin Name PA7 to PA0 PB7 to PB0 PC1 and PC0 PC2/SCK PC3/INT2 PC7 to PC4 AD7 to AD0 AB11 to AB8 PF7 to PF4 NMI INT1 Type No. 5 5 5 8 10 5 5 5 5 2 9 Pin Name RESET RD WR ALE STOP MODE0 MODE1 AN3 to AN0 AN7 to AN4 VAREF Type No. 2 4 4 4 2 11 11 7 12 13 Table 1-2 Pin Type No. for PD78C18 Pin Name PA7 to PA0 PB7 to PB0 PC1 and PC0 PC2/SCK PC3/INT2 PC7 to PC4 PD7 to PD0 PF7 to PF0 NMI INT1 Type No. 5-A 5-A 5-A 8-A 10-A 5-A 5 5 2 9 Pin Name RESET RD WR ALE STOP MODE0 MODE1 AN3 to AN0 AN7 to AN4 VAREF Type No. 2 4 4 4 2 11 11 7 12 13 9 PD78C17,78C18 (1) Type 1 VDD P- ch IN N- ch (2) Type 2 IN (3) Type 4 V DD output data P-ch OUT output disable N-ch (4) Type 4-A V DD output data P-ch OUT output disable N-ch 10 PD78C17,78C18 (5) Type 5 output data Type 4 output disable IN/OUT Type 1 (6) Type 5-A output data Type 4-A output disable IN/OUT Type 1 (7) Type 7 AV DD P-ch IN N-ch AV DD Sampling C AV SS Reference Voltage (from Voltage Tap of Serial Resistance String) + - (8) Type 8 output data output disable N-ch Type 5 IN/OUT N-ch Type 2 MCC 11 PD78C17,78C18 (9) Type 8-A output data output disable N-ch Type 5-A IN/OUT N-ch Type 2 MCC (10) Type 9 self bias enable IN Type 2 data (11) Type 10 output data output disable N-ch Type 5 IN/OUT N-ch self bias enable Type 9 MCC 12 PD78C17,78C18 (12) Type 10-A output data output disable N-ch Type 5-A IN/OUT N-ch self bias enable Type 9 MCC (13) Type 11 IN/OUT output data N-ch Type 1 (14) Type 12 IN Type 7 Type 2 Edge Detector 13 PD78C17,78C18 (15) Type 13 IN Type 1 STOP Mode P-ch AV SS 14 PD78C17,78C18 1.3 PIN MASK OPTIONS The PD78C18 has the following mask options, which can be selected bit-wise according to the application. Pin Name PA7 to PA0 PB7 to PB0 PC7 to PC0 Mask Options Pull-up resistor can be incorporated Cautions 1. 2. Zero-cross detection function will not operate properly if pull-up resistor is incorporated in PC3. The PD78C17 has no mask option. 5 1.4 UNUSED PIN CONNECTIONS Pin PA7 PB7 PC7 PD7 PF7 to to to to to PA0 PB0 PC0 PD0 PF0 Recommended Connection Connect to VSS or VDD via a resistor RD WR ALE STOP INT1, NMI AVDD AVAREF AVSS AN7 to AN0 Leave open Connect to VDD Connect to VSS or VDD Connect to VDD Connect to VSS Connect to AVSS or AVDD 15 PD78C17,78C18 2. INTERNAL BLOCK FUNCTIONS 2.1 REGISTERS The central registers are the sixteen 8-bit registers and four 16-bit registers shown in Fig. 2-1. Fig. 2-1 Register Configuration 15 PC SP 0 15 EA 7 V B D H 0 7 A C E L 0 0 MAIN 15 EA' 7 V' B' D' H' 0 7 A' C' E' L' 0 0 ALT (a) General registers (B, C, D, E, H, L) There are two sets of general registers (MAIN: B, C, D, E, H, L; ALT: B', C', D', E', H', L'). They function as auxiliary registers for the accumulator, and have a data pointer function as register pairs (BC, DE, HL; B'C', D'E', H'L'). In particular, four register pairs DE, D'E', HL, and H'L', have a base register function. When the two sets are used, if an interrupt occurs in one set, the register contents are saved into the other register set without saving them into the memory so that interrupt servicing can be carried out. The other set of registers can also be used as data pointer expansion registers. Two addressing modes, singlestep automatic increment/decrement modes and a two-step automatic increment mode, are available for the register pairs, DE, HL, D'E', and H'L', so that the processing time can be reduced. BC, DE, and HL can be simultaneously replaced with the ALT register by means of the EXX instruction. The HL register can be independently replaced with the ALT register by means of the EXH instruction. (b) Working register vector register (V) When a working area is set in the memory space, the high-order 8 bits of the memory address are selected using the V register and the low-order 8 bits are addressed by the immediate data in the instruction. Thus, the memory area specified with the V register can be used as working registers with a 256 x 8bit configuration. Because a working register can be specified with a 1-byte address field, program reduction is possible by using the working area for software flags, parameters, and counters. The V register can be replaced with the ALT register paired with an accumulator by means of the EXA instruction. 16 PD78C17,78C18 (c) Accumulator (A) In the PD78C17 and 78C18, because an accumulator type architecture is used, 8-bit data processing such as 8-bit arithmetic and logical operation instructions is mainly performed by this accumulator. This accumulator can be replaced with the ALT register paired with the vector register (V) by means of the EXA instruction. Expansion accumulator (EA) 16-bit data processing such as 16-bit arithmetic and logical operation instructions is mainly performed by EA. This accumulator can be replaced with the ALT register EA' by means of the EXA instruction. (d) (e) Program counter (PC) This is a 16-bit register which holds information on the next program address to be executed. This register is normally incremented automatically according to the number of bytes of the instruction to be fetched. When an instruction associated with a branch is executed, immediate data or register contents are loaded. RESET input clears this counter to 0000H. (f) Stack pointer (SP) This is a 16-bit register which holds the start address of the memory stack area (LIFO format). SP contents are decremented when a CALL or PUSH instruction is executed or an interrupt is generated, and incremented when a RETURN or POP instruction is executed. 2.2 ARITHMETIC LOGIC UNIT (ALU) ...16 BITS The ALU executes data processing such as 8-bit arithmetic and logical operations, shift and rotation, data processing such as 16-bit arithmetic and logical operations and shift operations, 8-bit multiplication and 16-bit by 8-bit division. 2.3 PROGRAM STATUS WORD (PSW) This word consists of 6 types of flags which are set/reset according to instruction execution results. Three of these flags (Z, HC, and CY) can be tested by an instruction. PSW contents are automatically saved to the stack when an interrupt (external, internal, or SOFTI instruction) is generated, and restored by the RETI instruction. RESET input resets all bits to (0). Fig. 2-2 PSW Configuration 7 0 6 Z 5 SK 4 HC 3 L1 2 L0 1 0 0 CY (a) Z (Zero) When the operation result is zero, this flag is set (1). In all other cases, it is reset (0). (b) SK (Skip) When the skip condition is satisfied, this flag is set (1). If the condition is not satisfied, it is reset (0). (c) HC (Half Carry) If an 8-bit operation generates a carry out of bit 3 or a borrow into bit 3, this flag is set (1). In all other cases, it is reset (0). (d) L1 When the "MVI A, byte" instruction is stacked, this flag is set (1). In all other cases, it is reset (0). 17 PD78C17,78C18 (e) L0 When the "MVI L, byte;LXI H, word" instruction is stacked, this flag is set (1). In all other cases, it is reset (0). (f) CY (Carry) When a 16-bit operation generates a carry out of or a borrow into bit 7 or 15, this flag is set (1). In all other cases, it is reset (0). When one of 35 types of ALU instructions, rotation instructions, or carry manipulation instructions is executed, various flags are affected as shown in Table 2-1. Table 2-1 Flag Operations Operation reg, memory immediate skip ADD ADDX ADI ADDW ADC ADCX ACI ADCW SUB SUBX SUI SUBW SBB SBBX SBI SBBW DADD DADC DSUB DSBB EADD ESUB ANA ANAX ANIW ANI ANAW ORA ORAX ORIW ORI ORAW XRA XRAX XRI XRAW DAN DOR DXR ADDNC ADDNCW ADDNCX ADINC SUBNB SUBNBW SUBNBX SUINB GTA GTAX GTIW GTI GTAW LTA LTAX LTIW LTI LTAW DADDNC DSUBNB DGT DLT ONA ONAX ONIW ONI ONAW OFFA OFFIW OFFI OFFAW OFFAX DON DOFF NEA NEAX NEIW NEI NEAW EQA EQAX EQIW EQI EQAW DNE DEQ INR INRW DCR DCRW DAA RLR RLL SLR SLL DRLR DRLL DSLR DSLL SLRC SLLC STC CLC MVI A, byte MVI L, byte LXI H, word BIT SK SKN SKIT SKN IT RETS Other All instructions D6 D5 D4 D3 D2 D0 Z SK HC L1 L0 CY 0 0 0 0q 0 0 0 0 q0 0 0 0 0 0 0q 0 0 0 q0q0 q0 q q0q0 q0q0 q0q1 q0q0 0 01 00 0q 1q ........ q q q q0 0q q1q0 q0q0 0q 0q 1 ........ 0 ........ q ........ Affected (Set or Reset) Set Reset No affected 18 PD78C17,78C18 2.4 MEMORY The PD78C17 and 78C18 can address a maximum of 64 Kbytes of memory. The memory maps are shown in Figs. 2-3 and 2-4. The external memory area and the internal RAM area can be freely used as program memory and data memory. Because the access timing for internal memory and external memory are the same, processing can be executed at high speeds. (a) Interrupt start addresses The interrupt start addresses are all fixed as follows: NMI ....................... 0004H INTT0/INTT1 ......... 0008H INT1/INT2 .............0010H INTE0/INTE1 ......... 0018H INTEIN/INTAD ...... 0020H INTSR/INTST ........0028H SOFTI ....................0060H (b) Call address table The call address of a 1-byte call instruction (CALT) can be stored in the 64-byte area (for 32 call addresses) from address 0080H to address 00BFH. (c) Specific memory area The reset start address, interrupt start addresses, and the call table are allocated to addresses 0000H to 00BFH, and this area takes account of these in use. Addresses 0800H to 0FFFH are directly addressable by a 2-byte call instruction (CALF). The PD78C18 has on-chip mask programmable ROM in addresses 0000H to 7FFFH. (d) Internal data memory area 1-Kbyte RAM is incorporated in addresses FC00H to FFFFH. The RAM contents are retained for 1-Kbyte internal data memory area in standby operation. (e) External memory area With the PD78C17, the external memory can be expanded in steps in 63-Kbyte area (0000H to FBFFH) by setting the MODE0 and MODE1 pins (see Table 2-3). With the PD78C18, the external memory can be expanded in steps in 31-Kbyte area (8000H to FBFFH) by setting the MEMORY MAPPING register (see Fig. 2-13). The external memory is accessed using AD7 to AD0 (multiplexed address/data bus), AB7 to AB0 (address bus), and the RD, WR, and ALE signals. Both programs and data can be stored in the external memory. (f) Working register area A 256-byte working register area can be set in any memory location (specified by the V register) and working register addressing is possible. 19 PD78C17,78C18 Fig. 2-3 PD78C17 Memory Map 0000H 0000H RESET 0004H NMI 0008H INTT0/INTT1 0010H External Memory 64512 x 8 Bits INT1/INT2 0018H INTE0/INTE1 0020H INTEIN/INTAD FBFFH FC00H Internal RAMNote 1024 x 8 Bits FFFFH Standby Area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H 0082H Call Table 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH LOW ADRS HIGH ADRS t = 31 Note Can only be used when the RAE bit of the MM register is 1. 20 PD78C17,78C18 Fig. 2-4 PD78C18 Memory Map 0000H 0000H RESET Internal ROM 32768 x 8 Bits 0004H NMI 0008H 7FFFH 8000H INTT0/INTT1 0010H INT1/INT2 External Memory 31744 x 8 Bits 0018H INTE0/INTE1 0020H INTEIN/INTAD FBFFH FC00H Internal RAMNote 1024 x 8 Bits FFFFH Standby Area 0028H INTSR/INTST 0060H SOFTI 0080H 0081H Call Table 0082H 0083H LOW ADRS HIGH ADRS LOW ADRS HIGH ADRS t=0 t=1 00BEH 00BFH 00C0H LOW ADRS HIGH ADRS t = 31 USER'S AREA Note Can only be used when the RAE bit of the MM register is 1. 7FFFH 21 PD78C17,78C18 2.5 PORT FUNCTIONS (1) PA7 to PA0 (PORT A) This is an 8-bit input/output port which has input/output buffer and output latch functions. Port A can be set as to input or output bit-wise using the MODE A register. And PD78C18 port A pull-up resistor specification is performed bit-wise by mask option. Port A is set as follows when setting the input port or after reset. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-5 Port A WRM MAn Latch WRP Internal Bus Output Latch Output Buffer V DD Mask OptionNote PAn RDO RDI Note Only PD78C18 (a) When specified as output port (MAn = 0) The output latch is effective, enabling data exchange by a transfer instruction between the output latch and the accumulator. Direct bit setting/resetting of output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Once data is written to the output latch, the data is held until a port A manipulation instruction is executed or the data is reset. Fig. 2-6 Port A Specified as Output Port V DD WRP Internal Bus Output Latch RDO Mask OptionNote PAn Note Only PD78C18 22 PD78C17,78C18 (b) When specified as input port (MAn = 1) PA line contents can be loaded into an accumulator by a transfer instruction. They can also be directly tested bit-wise by an arithmetic or logical operation instruction without the use of an accumulator. Fig. 2-7 Port A Specified as Input Port V DD WRP Output Latch Internal Bus Mask OptionNote PAn RDI Note Only PD78C18 Actual execution of an instruction which manipulates port A is performed in 8-bit units. If a port A read instruction (MOV A, PA) is executed, the input line contents of the port specified for input and the output latch contents of the port specified for output are loaded into an accumulator. When a port A write instruction (MOV PA, A) is executed, data is written to the output latch of both ports specified for input and output. However, the output latch contents of a bit specified as an input port cannot be loaded to the accumulator and are not output to an external pin (which functions as input pin), because the output buffer is off. * MODE A register (MA) 8-bit register which specifies port A input/output. Port A input/output can be specified bit-wise. If the MODE A register corresponding bit is set (1), this register is input, and if the bit is reset (0), this register is output. After RESET input or in the hardware STOP mode, all the bits are set, and port A is in the input mode resulting in the below status. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-8 MODE A Register Format 7 MA 7 6 MA 6 5 MA 5 4 MA 4 3 MA 3 2 MA 2 1 MA 1 0 MA 0 0 1 PAn = Output PAn = Input (n = 0 to 7) 23 PD78C17,78C18 (2) PB7 to PB0 (PORT B) Like port A, port B is an 8-bit input/output port with input/output buffer and output latch functions. Port B can be set as an input or output port bit-wise using the MODE B register (MB). PD78C18 port B pull-up resistor specification is performed bit-wise by mask option. Port B is set as follows when setting the input port or after reset. High-impedance : Without pull-up resistor High level : With pull-up resistor As with port A, direct bit setting/resetting of port B output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. * MODE B Register (MB) Like the MODE A register, the MODE B register is an 8-bit register which specifies port B input/ output bit-wise. After RESET input or in the hardware STOP mode, all the bits are set (1), and port B is in the input mode resulting in the status below. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-9 Mode B Register Format 7 MB 7 6 MB 6 5 MB 5 4 MB 4 3 MB 3 2 MB 2 1 0 MB 1 MB 0 0 1 PBn = Output PBn = Input (n = 0 to 7) 24 PD78C17,78C18 (3) PC7 to PC0 (PORT C) Port C (PC7 to PC0) is an 8-bit special input/output port which functions as various control signals as well as general-purpose input/output ports in which input/output is set bit-wise like port A. These are switched over bit-wise according to the setting of the MODE C register and MODE CONTROL C register as shown below. Table 2-2 Operation of PC7 to PC0 MCCn = 1 MCn = x TXD output RXD inpit SCK input/output INT2/TI input TO output CI input CO0 output CO1 output MCCn = 0 MCCn = 0 MCn = 1 Output Input Output Input Output Input Output Input Output Input Output Input Output Input Output Input (n = 0 to 7) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD78C18 port C pull-up resistor specification is performed bit-wise by mask option. In the operation when data is set in the general-purpose input/output ports, as with port A, direct bit setting/resetting/testing of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. * MODE CONTROL C Register (MCC) 8-bit register which specifies the port C port/ control signal input/output mode bit-wise. If the MODE CONTROL C register corresponding bits are set (1), PC7 to PC0 are in the control signal input/output mode, and if these are reset (0), in the port mode. After RESET input or in the hardware STOP mode, all the bits of the MODE CONTROL C register are reset (0), and the port mode is set. 25 PD78C17,78C18 Fig. 2-10 MODE CONTROL C Register Format 7 6 5 4 3 2 1 0 MCC7 MCC6 MCC5 MCC4 MCC3 MCC2 MCC1 MCC0 0 1 PC0 = Port mode PC0 = TXD output 0 1 PC1 = Port mode PC1 = RXD input 0 1 PC2= Port mode PC2 = SCK input/output 0 1 PC3 = Port mode PC3 = INT2/TI input 0 1 PC4 = Port mode PC4= TO output 0 1 PC5 = Port mode PC5 = CI input 0 1 PC6= Port mode PC6 = CO0 output 0 1 PC7 = Port mode PC7 = CO1 output 26 PD78C17,78C18 * MODE C register (MC) The MODE C register is an 8-bit register by which, like the MODE A register of port A, port C input/ output specification is performed bit-wise. Contents of the MODE C register corresponding to the bits set to the control mode by the MODE CONTROL C register are ignored. After RESET input or in the hardware STOP mode, all bits of the MODE C register are set (1). And this time, because all bits of the MODE CONTROL C register are reset (0), port C becomes an input port and the below state is set. High-impedance : Without pull-up resistor High level : With pull-up resistor Fig. 2-11 MODE C register Format 7 MC 7 6 MC 6 5 MC 5 4 MC 4 3 MC 3 2 MC 2 1 MC 1 0 MC 0 0 1 PCn = Output PCn = Input (n = 0 to 7) (4) PD7 to PD0 (PORT D) s PD78C17 Can be used for address/data bus. These have no functions as a port. s PD78C18 8-bit general-purpose input/output ports also used as multiplexed address/data bus. These ports can be specified for input/output in byte units (8-bit units) as general-purpose input/output ports, and function as multiplexed address/data bus when external expansion memory is connected. This switchover is performed by the MEMORY MAPPING register. In the operation when data is set in the general-purpose input/output ports, unless input/output is specified in byte units, as with port A, direct bit setting/resetting/testing of port F output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. 27 PD78C17,78C18 (5) PF7 to PF0 (PORT F) s PD78C17 General-purpose input/output ports also used as address bus. These pins function as address outputs corresponding to the size of externally installed memory according to the MODE0 and MODE1 pin settings. Pins which are not used for address output can be used for general-purpose input/output ports which have the same port function as for port A. Input/output setting is performed by the MODE F register. Table 2-3 Operation of PD78C17's PF7 to PF0 MODE1 0 0 1 1 MODE0 0 1 0 1 PF 7 Port Port PF 6 Port Port PF 5 Port PF 4 Port PF 3 AB11 AB11 PF 2 AB10 AB10 PF 1 AB9 AB9 PF 0 AB8 AB8 External Address Space 4 Kbytes 16 Kbytes AB13 AB12 Setting prohibited AB15 AB14 AB13 AB12 AB11 AB10 AB9 AB8 63 Kbytes When this is set as general-purpose input/output ports, as with port A, direct bit setting/resetting/ testing of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. * PD78C17 MEMORY MAPPING register (MM) A register which controls internal RAM access permission. Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not internal RAM is permitted. When internal RAM is used in external extension and external memory is used in the area, RAE bit is set to "0" and internal RAM access is prohibited. Contents of RAE bit is retained, even if RESET signal is input in the normal operation. However, at power-on reset, RAE bit is undefined and RAE bit should be initialized by an instruction. Fig. 2-12 PD78C17 MEMORY MAPPING Register Format 7 6 5 4 3 RAE 2 0 1 0 0 0 Internal RAM Access 0 1 Disable Enable 28 PD78C17,78C18 s PD78C18 8-bit general-purpose input/output ports also used as address bus. Can specify input/output bit-wise as general-purpose input/output ports, and address signal is output according to external extension memory size when the external expansion memory of 256 bytes or greater is accessed. This switchover is performed by the MEMORY MAPPING and MODE F registers. PF7 Port Port Port AB15 PF6 Port Port Port AB14 PF5 Port Port AB13 AB13 PF4 Port Port AB12 AB12 PF3 Port AB11 AB11 AB11 PF2 Port AB10 AB10 AB10 PF1 Port AB9 AB9 AB9 PF0 Port AB8 AB8 AB8 External Memory Maximum 256 bytes Maximum 4 Kbytes Maximum 16 Kbytes Maximum 31 Kbytes When this is set as general-purpose input/ourput ports, as with port A, direct bit setting/resetting/testing of port C output latch contents is possible by an arithmetic or logical operation instruction without the use of an accumulator. Data transfer to/from an accumulator is also possible. * PD78C18 MEMORY MAPPING register (MM) 4-bit register which specifies PD7 to PD0 and PF7 to PF0 port/extension mode and controls internal RAM access permission. Bits 0, 1, and 2 (MM0, MM1, MM2) in the MEMORY MAPPING register control specification of PD7 to PD0 port/extension mode, input/output, and PF7 to PF0 address line. When bits MM1 and MM2 in the MEMORY MAPPING register are "0", PD7 to PD0 and PF7 to PF0 are set as general-purpose input/output port, input/output of PD7 to PD0 is specified by MM0, and input/output of PF7 to PF0 is specified by the MODE F register. 4 types of external extension memory (256 bytes, 4 Kbytes, 16 Kbytes, and 31 Kbytes) can be selected, and ports which are not used for address line are used as general-purpose input/output ports. Bit 3 (RAE) of the MEMORY MAPPING register controls whether or not the access to internal RAM is permitted. When internal RAM is not used in external extension and external memory uses the area, RAE bit is set to "0" and internal RAM access is prohibited. After RESET input or in the hardware STOP mode, bits MM0, MM1, and MM2 of the MEMORY MAPPING register are reset (0), and PD7 to PD0 become input ports (high-impedance). Even if the RESET signal is input in the normal operation, contents of the RAE bit are retained. However, the RAE bit is undefined after power-on reset, the RAE bit should be initialized by an instruction. 29 PD78C17,78C18 Fig. 2-13 PD78C18 MEMORY MAPPING Register Format 7 6 5 4 3 RAE 2 MM2 1 MM1 0 MM0 000 00 01 10 11 11 PD7 to PD0 = Input port PF7 to PF0 = Port mode PD7 to PD0 = Output port 1 PF7 to PF0 = Port mode PD7 to PD0 = Extension 256 bytes 0 mode PF7 to PF0 = Port mode PD7 to PD0 = Extension 4 Kbytes PF3 to PF0 = 0 mode PF7 to PF4 = Port mode ExtenPD7 to PD0 = Extension sion 16 Kbytes PF5 to PF0 = mode 0 mode PF7 and PF6 = Port mode Extension 31 Kbytes PD7 to PD0 = 1 mode PF7 to PF0 = Single Port mode chip Internal RAM Access 0 1 Disable Enable * MODE F register (MF) The MODE F register specifies port F input/output in the same way as for the MODE A register in port A. However, contents of the MODE F register corresponding to port F bits specified as address line by the MEMORY MAPPING register are in the output mode. After RESET input or in the hardware STOP mode, all the bits of the MODE F register are set (1) and port F is an input port (high-impedance). Fig. 2-14 MODE F Register Format 7 MF 7 6 MF 6 5 MF 5 4 MF 4 3 MF 3 2 MF 2 1 MF 1 0 MF 0 0 1 PFn = Output PFn = Input (n = 0 to 7) 30 PD78C17,78C18 2.6 TIMER This is an interval timer which has two 8-bit timers (TIMER0, TIMER1). These are programmable independently. By cascading these can also be used as 16-bit interval timer, and can be used for counting TI input. The timer is composed of TIMER0 and TIMER1, as shown in 2-15, including 8-bit TIMER REG (TM0, TM1), 8bit COMPARATOR, 8-bit UPCOUNTER, and TIMER F/F. Input selection, timer operation and TO output are controlled by the timer mode register (TMM). In TIMER0, 12 (1 s: 12-MHz operation) and 384 (32 s: 12-MHz operation) internal clock and TI input are input. In TIMER1, not only these inputs but also TIMER0 match signal are input. Because TIMER0 operates in the same way as TIMER1, TIMER0 operation is described below. At first, a count value is set in TIMER REG0, and TIMER0 input and TIMER0 start data (bit 4 in the timer mode register = "0") are set in the timer mode register to start TIMER0. The UPCOUNTER is incremented one input at a time. The COMPARATOR always compares contents of the incremented UPCOUNTER with those of TIMER REG0, and if these match, the match signal (internal interrupt: INTT0) is generated. This match clears contents of UPCOUNTER and increment starts again from 00H. Therefore, the interval is set by count time, which is a count value set by TIMER REG0. This allows the timer to operate as an interval timer which generates interrupts repeatedly. By setting (1) bit 1 (MKT0) of the interrupt mask register (MKL), internal interrupt (INTT0) is disabled. The TO output has timers COMPARATOR match signal and TIMER F/F complemented by 3 (250 ns: 12-MHz operation) internal clocks, and can obtain a square wave which has a half period of the count time or 3. By setting the timer/event counter mode register (ETMM), this output can be used for the timer event counter reference time. By setting the serial mode register (SMH), the timer can be used as the serial clock (SCK) in serial interface. 31 PD78C17,78C18 Fig. 2-15 Timer Block Diagram 3 TIMER F/F PC4/TO TIMER0 PC3/TI TIMER1 Timer/Event Counter Serial Interface Clear 12 384 UPCOUNTER 12 Clear UPCOUNTER 384 COMPARATOR COMPARATOR TIMER REG 0 (TM0) INTT0 TIMER REG 1 (TM1) INTT1 Internal Bus Remarks 1. 2. 3. 3 = fXX x 1/3 12 = fXX x 1/12 384 = fXX x 1/384 Where, fXX = oscillation frequency (MHz) 32 PD78C17,78C18 (1) Timer mode register (TMM) This is an 8-bit register which controls TIMER0, TIMER1, and TIMER F/F operation (see Fig. 2-16). The timer mode register bits 0 and 1 (TF0, TF1) control the TIMER F/F operating mode, bits 2 and 3 (CK00, CK01) control TIMER0 input clock, bit 4 (TS0) controls TIMER0 operation. Bits 5 and 6 (CK10, CK11) control TIMER1 input clock, and bit 7 (TS1) controls TIMER1 operation. TS0 and TS1 bits clear these UPCOUNTERs to 00H by "1", and stop increment. By changing "1" to "0", the UPCOUNTER starts increment from 00H. The internal clock (3) divides the oscillator frequency by 3, the internal clock (12) divides it by 12, and the internal clock (384) divides it by 384. After RESET input, the timer mode register is set to FFH, the UPCOUNTERs in TIMER0 and TIMER1 are cleared in the suspended state, and TIMER F/F is reset. Fig. 2-16 Timer Mode Register (TMM) Format 7 TMM TS1 6 CK11 5 CK10 4 TS0 3 CK01 2 CK00 1 TF1 0 TF0 TIMER F/F Input, Operating Mode 0 0 1 1 0 1 0 1 TIMER0 COMPARATOR match signal TIMER1 COMPARATOR match signal Internal clock (3) TIMER F/F reset TIMER0 Input Clock 0 0 1 1 0 1 0 1 Internal clock (12) Internal clock (384) TI input Disable TIMER0 Operation 0 1 Increment Reset TIMER0 Input Clock 0 0 1 1 0 1 0 1 Internal clock (12) Internal clock (384) TI input TIMER0 COMPARATOR match signal TIMER1 Operation 0 1 Increment Reset 33 PD78C17,78C18 2.7 TIMER/EVENT COUNTER The PD78C17 and 78C18 have a 16-bit multi-function timer/event counter having the following functions. o o o o o o Interval timer External event counter Frequency measurement Pulse width measurement Programmable square wave output One pulse output The timer/event counters are composed of 16-bit timer/event counter upcounter (ECNT), timer/event counter capture register (ECPT), comparator, timer/event counter REG0 and REG1 (ETM0, ETM1), control circuits for I/O, interrupt, and clear. ECNT is a 16-bit upcounter which counts an input pulse, and cleared by the clear control circuit. The ECPT register is a 16-bit buffer register which retains the contents of ECNT. The timing to latch contents of ECNT by the ECPT register is the falling edge of CI input when input to ECNT is an internal clock, and is the falling edge of TO output when input to ECNT is CI input. The ETM0 and ETM1 registers are two 16-bit registers which set a number of counts and data is exchanged by 16-bit data transfer instructions via an extended accumulator. The comparator compares contents of ECNT with contents of the ETM0 and ETM1 registers, and if these match, a match signal is generated. The interrupt control circuit controls interrupts from the timer/event counter. The following interrupt sources are generated. These are generated by three signals: the ECNT and ETM0 register match signal (INTE0), the ECNT and ETM1 register match signal (INTE1), and the CI input or timer output (TO) falling edge (INTEIN). 34 PD78C17,78C18 Fig. 2-17 Timer/Event Counter Block Diagram Internal Bus Timer/event Counter Capture Reg. (ECPT) 12 PC5/CI Input Control Timer/event Counter Capture Reg. (ECNT) Clear Control Output Control PC7/CO1 Comparator Comparator PC6/CO0 TO Timer/event Counter REG1 (ETM1) Timer/event Counter REG0 (ETM0) CP0 CP1 Interrupt Control INTE0 INTE1 INTEIN Mode Register (ETMM, EOM) EIN Internal Bus Edge Detection Remarks 12 = fXX x 1/12, where fXX = oscillation frequency (MHz) 35 PD78C17,78C18 Next, using pulse width measurement as an example, the operation is described. This operation purpose is measurement for high-level width of external pulse input to CI. This is performed by setting the timer/event counter mode register (ETMM) to 09H. ECNT continues internal clock (12) count while CI is high. If the external pulse which is input to CI falls, the contents of ECNT are transferred to the ECPT register. ECNT is cleared and an internal interrupt (INTEIN) is generated (see Fig. 2-18). Therefore, using contents of the ECPT register and internal clock period, the pulse width is measured. Fig. 2-18 Pulse Width Measurement Reference Clock (12) CI Input ECNT Input EIN Interrupt Transfer ECNT contents to ECPT register Clear ECNT 36 PD78C17,78C18 The PD78C17 and 78C18 have an output control circuit which outputs pulses which can be changed in pulse width and period by interlocking with the timer/event counter. The output control circuit outputs are CO0 output and CO1 output. Because these share the same configuration, CO0 output is described. Fig. 2-19 shows the CO0 configuration. CO0 output is a master-slave type output. The first phase level F/F (LV0) retains the level which is output next, and the second phase output latch outputs the LV0 level to off-chip. By setting the timer/event counter output mode register (EOM), LV0 can be set/reset. LV0 has a level inversion pin (INV) and LV0 level can be inverted at the output time by setting the timer/event counter mode register. Timing when the output latch outputs LV0 level to off-chip is performed by output timing of the timer/event counter mode register setting. Fig. 2-19 Output Control Circuit Level Flipflop LRE0 LRE1 LD0 CP0 CP1 CI LO0 R Q S LV0 INV Output Latch D CK O PC6/CO0 37 PD78C17,78C18 Next, the operation which outputs a square wave to the CO0 pin is described. At first, after ECNT is cleared, a count value (ETM0 < ETM1) is set in the ETM0 and ETM1 registers, and data for LV0 initial status specification and to enable LV0 level inversion is set in the timer/event counter output mode register. In the timer/event counter mode register, by setting an input to ECNT to 12 (1 s: 12-MHz operation) internal clock, the ECNT clear mode to the ECNT and ETM1 register match signal, and CO0 pin output timing to the ECNT and ETM0 register match signal or ECNT and ETM1 register match signal, the timer/event counter starts operation. ECNT is incremented one 12 internal clock at a time, the comparator compares incremented ECNT with the ETM0 and ETM1 registers, and if these match, the match signal (CP0, CP1) is generated. By this match signal, LV0 level is output to the CO0 pin, and LV0 level is inverted. ECNT is cleared by the ECNT and ETM1 register match signal (CP1), ECNT increments again from 0000H, and the above-mentioned steps are repeated (see Fig. 2-20). Therefore, a programmable square wave which has the ETM0 and ETM1 register count as a pulse width is output. Fig. 2-20 Square Wave Output Reference Clock (12) 0 CP0 m n0 m n0 CP1 CO0 Start Remarks ETM0 register = m ETM1 register = n (m < n: m and n are count values.) 38 PD78C17,78C18 (1) Timer/event counter mode register (ETMM) This is an 8-bit register which controls the timer/event counter (see Fig. 2-21). The timer/event counter mode register bits 0 and 1 (ET0, ET1) control the timer event counter upcounter (ECNT) input clock, bits 2 and 3 (EM0, EM1) control the ECNT clear mode, bits 4 and 5 (CO00, CO01) control output timing when the output latch contents are output to the counter output0 (CO0). Bits 6 and 7 (CO10, CO11) control CO1 output timing. The internal clock (12) divides the oscillation frequency by 12. After RESET input or in the hardware STOP mode, the timer/event counter mode register is reset to 00H. Fig. 2-21 Timer/Event Counter Mode Register Format 7 ETMM 6 5 4 3 EM 1 2 EM 0 1 ET 1 0 ET 0 CO11 CO10 CO01 CO00 ECNT Input Clock 0 0 1 1 0 1 0 1 Internal clock (12) 12 while CI input is in the high level CI input CI input while TO is in the high level ECNT Clear Mode 0 0 1 1 0 1 0 1 Stop after clear Free running Clear a full count at a time Clear at the fall of CI input (ET1 = 0) Clear the fall of TO (ET1 = 1) Clear by matching ECNT and ETM1 CO0 Output Timing 0 0 1 1 0 1 0 1 ECNT and ETM0 match Setting prohibited ECNT and ETM0 match, or CI input fall ECNT and ETM0 match, or ECNT and ETM1 match CO1 Output Timing 0 0 1 1 0 1 0 1 ECNT and ETM1 match Setting prohibited ECNT and ETM1 match, or CI input fall ECNT and ETM0 match, or ECNT and ETM1 match 39 PD78C17,78C18 (2) Timer/event counter output mode register (EOM) This is an 8-bit register which controls the timer/event counters CO0 and CO1 (Counter Output 0, 1) operating mode. The timer/event counter output mode register bits 0 and 4 (LO0, LO1) control whether or not LV0 and LV1 level are output to the CO0 and CO1 pins, bits 1 and 5 (LD0, LD1) control whether or not LV0 and LV1 level are inverted at an output timing specified by the timer/event counter mode register, bits 2, 3, 6, and 7 (LRE0, LRE1, LRE2, LRE3) control LV0 and LV1 setting/resetting. Bits LO0, LO1, LRE0, LRE1, LRE2, and LRE3 are automatically reset (0) after individual operations. After RESET input or in the hardware STOP mode, the timer/event counter output mode register is reset to 00H. Fig. 2-22 Timer/Event Counter Output Mode Register (EOM) Format 7 LRE3 6 LRE2 5 LD 1 4 LO 1 3 LRE1 2 LRE0 1 LD 0 0 LO 0 LV0 Data Output 0 1 No operation Output contents of LV0 LV0 Level Inversion 0 1 Disable Enable LV0 Set/Reset 0 0 1 1 0 1 0 1 No operation Resets LV0 Sets LV0 Setting prohibited LV1Data Output 0 1 No operation Output contents of LV1 LV1 Level Inversion 0 1 Disable Enable LV1 Set/Reset 0 0 1 1 0 1 0 1 No operation Resets LV1 Sets LV1 Setting prohibited 40 PD78C17,78C18 2.8 SERIAL INTERFACE The PD78C17 and 78C18 have the serial interface using the transmit/receive method by start/stop bit. The three types of operating modes are shown below. * Asynchronous (start-stop) mode : Establishes data bit synchronization and character synchronization by start bit. * Synchronous mode * I/O interface mode : Data transfer is performed in synchronization with the serial clock. : As for serial data transfer in the PD7801/78C06A etc., data transfer is performed in synchronization with the serial clock. The serial interface block is composed of the serial data input (RxD), serial data output (TxD), 3 serial clock input/output (SCK) pins, transfer control block, two 8-bit serial registers for transmission and reception, and 8bit transmission buffer and reception buffer (see Fig. 2-23). As the serial registers and buffers for transmission and reception are provided, transmission or reception is individually performed (full-duplex double buffer transmitter/receiver). However, the serial clock (SCK) is shared in transmission and reception, and half-duplex transmission/ reception is performed in the synchronous mode and I/O mode. Fig. 2-23 Serial Interface Block Diagram Internal Bus INTSR Receive Buffer (RXB) Serial Mode Register (SML, SMH) Transmit Buffer (TXB) INTST PC1/RxD Serial Register (SP) Serial Register (PS) Reception Control ER Transmission Control PC2/SCK 24 384 TO Output SK1, SK2 PC0/TxD Remarks 24 = fXX x 1/24 384 = fXX x 1/384 Where, fXX = oscillation frequency (MHz) 41 PD78C17,78C18 (1) Asynchronous mode In case of the asynchronous mode, clock rate, character length, number of stop bits, parity enable, and odd or even parity specifications can be controlled by the serial mode register (SML). Transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH). If data is written to the transmission buffer by the "MOV TXB, A" instruction and preceding data transfer is terminated, contents of the transmission buffer are transferred to the serial register automatically. The start bit (1 bit), parity bit (odd/even number, no parity), and stop bit (1 or 2 bits) are automatically added to data which is transferred to the serial register. And this data is transmitted from the TxD pin starting from the least significant bit (LSB). If the transmit buffer is empty, the internal interrupt (INTST) is generated. Transmission data is transmitted from the TxD pin at the fall of SCK in the transfer speed of x1, x1/16, or x1/64 serial clock (SCK). The maximum data transfer speed in transmission is set by SCK and clock rate in 12-MHz operation as shown below. SCK Clock Rate x1 SCK Internal Clock Data Transfer Speed 500 kbps SCK External Clock Data Transfer Speed 660 kbps 500 kHz 660 kHz x16 2 MHz x64 125 kbps 2 MHz 31.25 kbps 125 kbps 31.25 kbps When TxE is "0" or the serial register has no transmitted data, the TxD pin is in the marking state (1). By setting bit 2 (MKST) of the interrupt mask register (MKH), the internal interrupt (INTST) is disabled. Fig. 2-24 Asynchronous Data Format Start Bit D0 D1 DN Parity Bit N = 6, 7 Stop Bit 42 PD78C17,78C18 Fig. 2-25 Serial Mode Register Format in Asynchronous Mode 7 SML S2 6 S1 5 EP 4 PEN 3 L2 2 L1 1 B2 0 B1 Clock Rate 0 1 1 1 0 1 x1 x16 x64 Character Length 0 0 1 1 0 1 0 1 Setting prohibited Setting prohibited 7 bits 8 bits Parity Enable 0 1 Disable Enable Even Parity Generation/Check 0 1 Odd number Even number Number of Stop Bits 0 0 1 1 0 1 0 1 Setting prohibited 1 bit Setting prohibited 2 bits 7 SMH 0 6 0 5 0 4 0 3 RxE 2 TxE 1 SK2 0 SK1 SCK Selection 0 0 1 1 0 1 0 1 Internal clock (TO output) Internal clock (384) Internal clock (24) External clock Transmission Enable 0 1 Disable Enable Reception Enable 0 1 Disable Enable 43 PD78C17,78C18 Receive operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH). The start bit is confirmed by detecting the low level of RxD input and the low level after 1 or 2 bits. Reception is performed by sampling character bit, parity bit, and stop bit following the low level. When data specified in the serial register from RxD is input, data is transferred to the receive buffer. If the receive buffer is full, the internal interrupt (INTSR) is generated. By setting (1) bit 1 (MKSR) of the interrupt mask register (MKH), the internal interrupt (INTSR) is disabled. In reception, odd or even parity is checked (when PEN bit = 1). If data do not match (parity error), if stop bit is low (framing error), or if the next data is transferred to the receive buffer when the receive buffer is full (overrun error), the error flag is set (1). However, because error interrupt mechanism is not provided, test is executed by the skip instruction (SKIT, SKNIT). The serial clock (SCK) can be selected as an external or internal clock by the serial mode register (SMH). Three types of 24, 384, or TO outputs can be selected as internal clock. This clock can be output to offchip. Or the external serial clock can be input. By using the internal clock (TO output) as SCK, the data transfer speed can be flexibly changed by program. The maximum data transfer speed in reception is set by SCK and the clock rate in 12-MHz operation as shown below. SCK Clock Rate x1 Note2 Internal Clock SCK Data Transfer Speed 500 kbps SCK External Clock Data Transfer Speed 660 kbps 1 MbpsNote1 125 kbps 2 MHz 500 kHz 660 kHz 1 MHz x16 2 MHz x64 125 kbps 31.25 kbps 31.25 kbps Notes 1. If data of transfer speed 660 kbps to 1 Mbps is received, 2 stop bits are required. 2. In x1 clock rate, RxD and SCK synchronization needs to be externally established. For an example, when data is transferred in the data transfer speed of 110 to 9600 bps, when the timer input clock is set as internal clock (12), the timer count value (C) is shown below. Oscillation Frequency (MHz) Data Transfer N Speed (bps) 9600 C = 4800 2400 1200 600 300 150 110 7.3728 16 2 4 C= 8 16 32 64 128 175 64 - 1 2 4 8 16 32 44 C= 16 11.0592 64 3 6 12 24 48 96 192 262 - - 3 6 12 24 48 65 C= 16 14.7456 64 4 8 16 32 64 128 256 370 C= 1 2 4 8 16 32 64 88 C= 44 PD78C17,78C18 (2) Synchronous mode In the synchronous mode, data transfer is performed with 8-bit character length fixed, and with no parity bit. Therefore, the serial mode register (SML) is set to 0CH (see Fig. 2-26). Transmission operation is enabled by setting (1) bit 3 (TxE) of the serial mode register (SMH). If data is written to the transmit buffer by the "MOV TXB, A" instruction and preceding data transfer is terminated, the contents of the transmit buffer are automatically transferred to the serial register and converted to serial data, and data starting from LSB are transmitted from TxD at the falling edge of SCK. The serial data is transferred in the same rate as for SCK. Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and maximum 1 Mbps when an external clock is used (12-MHz operation). When data is transferred from the transmit buffer to the serial register and the transmit buffer is empty, the internal interrupt (INTST) is generated. When TxE is "0" or the serial register has no transmitted data, the TxD pin is in the marking state (1). Fig. 2-26 Serial Mode Register Format in Synchronous Mode 7 SML 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0 Synchronous Operation Character Length 8-Bit Fixed Parity Disable 7 SMH 0 6 0 5 0 4 SE 3 RxE 2 TxE 1 SK 2 0 SK 1 SCK Selection 0 0 1 1 0 1 0 1 Internal clock (TO output) Internal clock (384) Internal clock (24) External clock Transmission Enable 0 1 Disable Enable Reception Enable 0 1 Disable Enable Search Mode 0 1 Disable Enable 45 PD78C17,78C18 In the synchronous mode, 2 types of receive operation can be selected. This mode can be controlled by SE bit of the serial mode register (SMH). By setting SE bit (1), the search mode is set. On each 1-bit reception from the RxD pin, the contents of the serial register are transferred to the receive buffer and the internal interrupt (INTSR) is generated. Because the PD78C17(A)/78C18(A) don't have a synchronous character detection circuit by hardware, a synchronous character detection is required by software. If receive synchronization is established after a synchronous character is detected, SE bit is reset (0). By resetting the SE bit, the character mode is set. On each 8-bit data reception, the contents of the serial register are transferred to the receive buffer and the internal interrupt (INTSR) is generated. By setting (1) MKSR bit of the interrupt mask register, the internal interrupt (INTSR) is disabled. In the synchronous mode, data is output from TxD at the falling edge of SCK, and data is input from RxD at the rising edge of SCK. SCK can be selected as an internal clock or external clock by setting the serial mode register (SMH). Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and maximum 660 kbps when an external clock is used (12-MHz operation). 46 PD78C17,78C18 (3) I/O interface mode When input/output is extended to off-chip or I/O controllers (A/D converter, liquid crystal display controller, etc.) are connected to this chip, this mode is effective. In the I/O interface mode, data transfer is performed starting from the most significant bit (MSB) with 8-bit character length fixed, and with no parity bits. Therefore, the serial mode register (SML) should be set to 0CH and bit 5 (IOE) of the serial mode register (SMH) is set to "1". This mode establishes synchronization by controlled SCK (8 cycles of the serial clock) and SCK should be high except during data transfer. The transmission operation is enabled by setting (1) bit 2 (TxE) of the serial mode register (SMH). If data is written by the "MOV TXB, A" instruction, data is transferred to the serial register automatically, and is output from TxD at the falling edge of controlled SCK. The transmit buffer is empty, the internal interrupt (INTST) is generated. Data transfer speed in transmission is maximum 500 kbps when an internal clock is used for SCK and maximum 1 Mbps when an external clock is used (12-MHz operation). The reception operation is enabled by setting (1) bit 3 (RxE) of the serial mode register (SMH), and receive data is input to the serial register at the rising edge of controlled SCK. When the serial register receives 8-bit data, data is transferred from the serial register to the receive buffer and the internal interrupt (INTSR) is generated. SCK can be selected as an internal clock or external clock by the serial mode register (SMH). Data transfer speed in reception is maximum 500 kbps when an internal clock is used for SCK and maximum 660 kbps when an external clock is used for SCK (12-MHz operation). 6 states or more is required in 8th SCK high-level width. 47 PD78C17,78C18 Fig. 2-27 Serial Mode Register Format in I/O Interface Mode 7 SML 0 6 0 5 0 4 0 3 1 2 1 1 0 0 0 Synchronous Operation Character Length 8-Bit Fixed Parity Disable 7 SMH 0 6 TSK 5 1 4 0 3 RxE 2 TxE 1 SK 2 0 SK 1 SCK Selection 0 0 1 1 0 1 0 1 Internal clock (TO output) Internal clock (384) Internal clock (24) External clock Transmission Enable 0 1 Disable Enable Reception Enable 0 1 Disable Enable I/O Interface Mode SCK Trigger 0 1 Disable Enable 48 PD78C17,78C18 (4) Serial mode register (SML, SMH) These are two 8-bit registers which control the serial interface operation (see Figs. 2-28 and 2-29). The serial mode low register (SML) bits 0 and 1 (B1, B2) control switchover of the asynchronous mode and synchronous operation and clock rate in the asynchronous mode, bits 2 and 3 (L1, L2) control character length, bit 4 (PEN) controls parity enable, bit 5 (EP) controls odd or even parity, and bits 6 and 7 (S1, S2) control a number of stop bits. After RESET input or in the hardware STOP mode, the serial mode low register (SML) is set to 48H. The serial mode high register (SMH) bits 0 and 1 (SK1, SK2) control whether an internal clock or external clock is used as the serial clock (SCK), bit 2 (TxE) controls the transmission operation, bit 3 (RxE) controls the reception operation, bit 4 (SE) controls whether or not the search mode is set in the synchronous mode. Bit 5 (IOE) controls whether the synchronous mode or I/O interface mode is set, and bit 6 (TSK) starts the serial clock when data is received using the internal clock in the I/O interface mode. The TSK bit is automatically reset (0) after the serial clock starts. When the serial clock is specified as an internal clock, the SCK value is determined by the following expressions. Internal clock (24): SCK = fXX/24 Internal clock (384): SCK = fXX/384 Internal clock (TO output): Timer input clock is 12: SCK = fXX/(24 x C) Timer input clock is 384: SCK = fXX/(768 x C) TIMER F/F input is 3: SCK = fXX/6 However, fXX is set in the oscillation frequency, SCK is set in the serial clock, and C is set in the timer count value. When TIMER F/F input is 3 in case of the internal clock (TO output), the asynchronous mode can only be used when the clock rate is 16 or 64. After RESET input or in the hardware STOP mode, the serial mode high register (SMH) is reset to 00H. 49 PD78C17,78C18 Fig. 2-28 Serial Mode Low Register (SML) Format 7 S2 6 S1 5 EP 4 PEN 3 L2 2 L1 1 B2 0 B1 Clock Rate 0 0 1 1 0 1 0 1 Synchronous Operation x1 x 16 x 64 Character Length 0 0 1 1 0 1 0 1 Setting prohibited Setting prohibited 7 bits 8 bits Parity Enable 0 1 Disable Enable Even Parity Generation/Check 0 1 Odd number Even number Number of Stop Bits 0 0 1 1 0 1 0 1 Setting prohibited 1 bit Setting prohibited 2 bits 50 PD78C17,78C18 Fig. 2-29 Serial Mode High Register (SMH) Format 7 0 6 TSK 5 IOE 4 SE 3 RxE 2 TxE 1 SK 2 0 SK 1 SCK Selection 0 0 1 1 0 1 0 1 Internal clock (TO output) Internal clock (384) Internal clock (24) External clock Transmission Enable 0 1 Disable Enable Reception Enable 0 1 Disable Enable Search Mode 0 1 Disable Enable I/O interface Mode 0 1 Disable Enable SCK Trigger 0 1 Disable Enable 51 PD78C17,78C18 2.9 ANALOG/DIGITAL CONVERTER The PD78C17 and 78C18 have on-chip 8-bit high-speed and high-resolution analog/digital (A/D) converter with 8-multiplexed analog input (AN7 to AN0), and 4 "Conversion Result" registers (CR0 to CR3) to retain a conversion result. This A/D converter uses the successive approximation method. In the A/D converter operation, either the scan mode or select mode can be selected by software. In the select mode, one of analog inputs is selected by the A/D channel mode register before starting A/D conversion. Conversion values are stored to CR0 through CR3 sequentially. In the scan mode, Analog conversion values AN0 to AN3 or AN4 to AN7 are stored to CR0 through CR3 sequentially. This mode switchover is specified by the A/D channel mode register. In case of the select mode, one of the analog inputs is selected by the A/D channel mode register and the A/ D conversion starts. Conversion values are stored to CR0 through CR3 sequentially. When four CR registers are set to conversion values, the internal interrupt (INTAD) is generated. The A/D converter continues A/D conversion and sequential storage of conversion values beginning with CR0 until the A/D channel mode register is changed. In case of the scan mode, the analog input AN0 to AN3 (ANI2 = 0) or AN4 to AN7 (ANI2 = 1) can be selected. If bit 3 (ANI2) of the A/D channel mode register is set to "0", analog inputs AN0, AN1, AN2, AN3 and AN0 are selected in that order. These input A/D conversion values CR0, CR1, CR2, CR3, and CR0 are stored in that order. If ANI2 of the A/D channel mode register is set to "1", analog inputs AN4, AN5, AN6, AN7, and AN4 are selected in that order, and these input A/D conversion values CR0, CR1, CR2, CR3, and CR0 in that order. In the scan mode, like in the select mode, when four CR registers are set to conversion values, the internal interrupt (INTAD) is generated. In the scan mode, too, the above-mentioned operation is repeated until the A/D channel mode register is changed. By setting (1) bit 0 (MKAD) of the interrupt mask register (MKH), the internal interrupt (INTAD) is disabled. 52 PD78C17,78C18 Fig. 2-30 A/D Converter Block Diagram AV DD AV SS V AREF AN0 AN1 MULTIPLEXER AN2 AN3 AN4 AN5 AN6 AN7 8 CR0 8 CR1 8 CR2 8 CR3 A/D CONVERTER 8 8 8 8 8 Internal Bus Caution Capacitors should be connected to the analog input pins and reference voltage input pins in order to prevent mulfunction due to noise. Analog Input 100 to 1000 pF AN n PD78C17 PD78C18 Reference Voltage Input 100 to 1000 pF V AREF V SS AV SS 53 PD78C17,78C18 (1) A/D channel mode register (ANM) This is an 8-bit register which controls A/D converter operation. Bit 0 (MS) of the A/D channel mode register controls the operating mode, bits 1, 2, and 3 (ANI0, ANI1, ANI2) controls A/D conversion input, and bit 4 (FR) controls A/D operation according to change of the oscillator frequency. In the A/D channel mode register, the operating mode specification is written, and the contents of this register are read. Therefore, in the A/D interrupt generation, analog input data distinction is possible. After RESET input or in the hardware STOP mode, the A/D channel mode register is set to 00H. Fig. 2-31 A/D Channel Mode Register Format 7 6 5 4 FR 3 ANI2 2 ANI1 1 ANI0 0 MS Operating Mode Specification 0 1 Scan mode Select mode Analog Input Specification 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 0 1 Oscillator frequency > 9 MHz (192 states) Oscillator frequency 9 MHz (144 states) (2) A/D converter operation control method The A/D converter can stop conversion operation by controlling the VAREF input voltage. If a voltage greater than VIH1 is input to the VAREF pin, the A/D converter starts conversion operation and the conversion results are guaranteed in VAREF = 3.4 V to AVDD. If the VAREF pin input voltage is set to less than VIL1 during the conversion operation, the A/D converter conversion operation stops. At this time, contents of CR0 to CR3 are undefined. Even if the VAREF input voltage is changed for A/D converter stop control, the A/D channel mode register (ANM) is not affected. Therefore, if the VAREF input voltage is greater than 3.4 V, the A/D converter restarts operation beginning with storage of conversion values to CR0 in the mode directly before the stop state is set. Even if the VAREF input voltage level is changed, the detection function of AN4 to AN7 input edge is not affected. Caution When VAREF is low, inputs AN0 to AN7 in the range of AVSS to AVDD are necessary. 54 PD78C17,78C18 2.10 ZERO-CROSS DETECTOR The INT1 pin and INT2/TI (shared as PC3) pin can be made to execute zero-cross detection operations by setting the zero-cross mode register. The zero-cross detector has a self-bias type high-gain amplifier. It biases the input to the switching point and generates digital displacement in response to a small input displacement. Fig. 2-32 Zero-Cross Detector PD78C17, 78C18 External Capacitor AC Input Signal INT 1 INT 2 / TI To Internal Circuit 1 F Self Bias Circuit enable The zero-cross detector detects a negative-to-positive or positive-to-negative transition of the AC signal input through an external capacitor and generates a digital pulse which changes from 0 to 1 or 1 to 0 at each transition point. Fig. 2-33 Zero-Cross Detection Signal AC Input signal Zero-Cross Detection Signal 55 PD78C17,78C18 A digital pulse generated in the zero-cross detector of the INT1 pin is sent to the interrupt control circuit. The INTF1 interrupt request flag is set at the zero-cross point from the negative to the positive state of the AC signal (rising edge), and if INT1 interrupt is enabled, interrupt servicing is started. A digital pulse generated in the INT2/TI pin zero-cross detector is sent to the interrupt control circuit and interrupt servicing can be started at the zero-cross point from the positive to the negative state of the AC signal (falling edge) as with the INT1 pin, and can also be used as a timer input clock. The format of the zero-cross mode register (ZCM), which controls self-bias for zero-cross detection of the INT1 and INT2/TI pins, is shown in Fig. 2-34. Fig. 2-34 Zero-Cross Mode Register Format 7 ZCM 6 5 4 3 2 ZC2 1 ZC1 0 INT1 Pin 0 1 Does not generate self-bias Generates self-bias INT2/T1 Pin 0 1 Does not generate self bias Generates self-bias When the ZC1 and ZC2 bits of the zero-cross mode register are set to "0", a self-bias for zero-cross detection of each pin is not generated and each pin responds as a normal digital input. When the ZC1 and ZC2 bits are set to "1", a self-bias is generated and an AC input signal zero-cross can be detected by connecting a capacitor to each pin. Each pin with ZC1 and ZC2 bits set to "1" can be directly driven without the use of an external capacitor. In this case, each pin responds as a digital input. However, an input load current is necessary and an external circuit output driver must be considered. Thus, when no zero-cross detection is executed and each pin is used simply as an interrupt input or timer input, the ZC1 and ZC2 bits of the zero-cross mode register should be set to "0". RESET input sets both the ZC1 and ZC2 bits to "1" and a self-bias is generated. The zero-cross function of the INT2/TI (shared as PC3) pin can operate only when the control mode is specified by the MODE CONTROL C register (MCC). In the port mode, the zero-cross detection function does not operate. Caution Unlike other CMOS circuits, a supply current is always present in the zero-cross detector because of its operation points. This also applies in the standby modes (HALT and software/hardware STOP modes). Thus, when the zero-cross detector is operated (with self-bias generation: ZCX = 1), slightly more current flows than without zero-cross detector operation, and its effect is greater in the software/hardware STOP mode. 56 PD78C17,78C18 3. INTERRUPT FUNCTIONS There are 3 kinds of external interrupt request and 8 kinds of internal interrupt requests. The 11 kinds of interrupt requests are divided into 6 groups, each of which is assigned a different priority and interrupt address. The priority of these interrupt sources and interrupt addresses are as follows. Priority 1 Interrupt Address 4 NMI Interrupt Request Falling edge External/ Internal External 2 8 INTT0 INTT1 Match signal from TIMER0 Match signal from TIMER1 Rising edge Falling edge Match signal from timer/event counter Match signal from timer/event counter Internal 3 16 INT1 INT2 External 4 24 INTE0 INTE1 Internal 5 32 INTEIN CI pin or TO fall signal INTAD A/D converter interrupt Serial reception interrupt Serial transmission interrupt Internal 6 40 INTSR INTST Internal 57 PD78C17,78C18 3.1 INTERRUPT CONTROL CIRCUIT CONFIGURATION The interrupt control circuit consists of a request register, a mask register, a priority control, a test control, an interrupt enable F/F, and a test flag register (see Fig. 3-1). Fig. 3-1 Interrupt Control Circuit Block Diagram NMI INTT0 REQUEST INTT1 INT1 INT2 INTE0 INTE1 INTEIN INTAD INTSR INTST INTFNMI TEST CONTROL T.F Skip Control INTFNMI MASK REGISTER ENABLE EI PRIORITY CONTROL INTFNMI DI S R Q SOFTI REGISTER Interrupt Generation OV ER SB AN7 to AN4 TEST FLAG REGISTER T.F SOFTI INT. ADR Internal Bus 58 PD78C17,78C18 (a) REQUEST REGISTER This register consists of 11 interrupt request flags which are set by the different interrupt requests. A flag is reset when an interrupt request is acknowledged or a skip instruction (SKIT or SKNIT) is executed. RESET input resets all flags. There are 11 types of interrupt request flags. * INTFNMI Set (1) by a falling edge input to the NMI pin. Unlike other interrupt request flags, this flag cannot be tested by a skip instruction. * INTFT0 Set (1) by TIMER0 COMPARATOR match signal. * INTFT1 Set (1) by TIMER1 COMPARATOR match signal. * INTF1 Set (1) by a rising edge input to the INT1 pin. * INTF2 Set (1) by a falling edge input to the INT2 pin. * INTFE0 Set (1) by a match signal when timer/event counter ECNT and ETM0 register contents match. * INTFE1 Set (1) by a match signal when timer/event counter ECNT and ETM1 register contents match. * INTFEIN Set (1) by a falling edge of the timer/event counter CI input or timer output (TO). * INTFAD Set (1) when A/D converter conversion values are transferred to the four registers CR0 to CR3. * INTFSR Set (1) when the serial interface receive buffer becomes full. * INTFST Set (1) when the serial interface transmit buffer becomes empty. (b) MASK REGISTER This is a 10-bit mask register which handles all interrupt requests except non-maskable interrupts (NMI). It can be set (1) or reset (0) bit-wise by an instruction. An interrupt request is masked (disabled) or enabled when the corresponding bit of the mask register is "1" or "0", respectively. All bits of the mask register are set by RESET input and all interrupt requests except non-maskable interrupts are masked. All bits of the mask register are set in the hardware STOP mode. 59 PD78C17,78C18 Fig. 3-2 Mask Register (MKL, MKH) Format 7 MKL MKEIN 6 MKE1 5 MKE0 4 MK2 3 MK1 2 MKT1 1 MKT0 0 ---- 0 1 INTT0 mask release INTT0 mask 0 1 INTT1 mask release INTT1 mask 0 1 INT1 mask release INT1 mask 0 1 INT2 mask release INT2 mask 0 1 INTE0 mask release INTE0 mask 0 1 INTE1 mask release INTE1 mask 0 1 INTEIN mask release INTEIN mask 7 MKH ---- 6 ---- 5 ---- 4 ---- 3 ---- 2 MKST 1 MKSR 0 MKAD 0 1 INTAD mask release INTAD mask 0 1 INTSR mask release INTSR mask 0 1 INTST mask release INTST mask 60 PD78C17,78C18 (c) PRIORITY CONTROL circuit This circuit controls the 6 priority levels described earlier. If two or more interrupt request flags are set simultaneously, the interrupt with the highest priority according to the priority is acknowledged. (d) TEST CONTROL circuit This circuit comes into operation when a skip instruction (SKIT or SKNIT) is executed to test interrupt request flags (except INTFNMI) for each interrupt source, NMI pin states, and test flags. (e) INTERRUPT ENABLE F/F (IE F/F) This is a flip-flop which is set by the EI instruction and reset by the DI instruction. This flip-flop is reset when an interrupt is acknowledged, and by RESET input, too. Interrupts are enabled when this flip-flop is set, and disabled when it is reset. (f) TEST FLAG REGISTER This register consists of 7 test flags which do not generate interrupt requests. These flags are tested or reset by the skip instructions (SKIT, SKNIT). * OV Set (1) when the timer/event counter ECNT overflows. * ER Set (1) in the event of a parity error, framing error or overrun error in serial interface. * SB Set (1) if VDD pin increases from a level lower than specified to a level higher than specified. * AN7 to AN4 Set (1) by a falling edge input to pins AN7 to AN4. 3.2 NON-MASKABLE INTERRUPT OPERATION When the interrupt request flag (INTFNMI) is set by a falling edge input to the NMI pin, a non-maskable interrupt is acknowledged by means of the following procedure irrespective of the EI/DI state (see Fig. 3-3). (i) A check is made to see if INTFNMI is set at the end of each instruction. If INTFNMI is set, a nonmaskable interrupt is acknowledged and INTFNMI is reset. (ii) When the non-maskable interrupt is acknowledged, the IE F/F is reset and all interrupts except for nonmaskable interrupts and the SOFTI instruction are placed in the disabled state (DI state). (iii) PSW, PC high byte, and PC low byte are saved into the stack memory in that order. (iv) The program jumps to the interrupt address (0004H). These interrupt operations are automatically carried out in 16 states. The interrupt request flag (INTFNMI) cannot be tested by the skip instruction. However, the NMI pin status can be tested by the skip instruction (SKIT NMI, SKNIT NMI). Therefore, by testing the NMI pin status with the skip instructions in several times in the non-maskable interrupt service routine, noise of comparatively long period or periodical noise can be removed. The NMI pin status is not changed even if the status is tested by the skip instruction. 61 PD78C17,78C18 Fig. 3-3 Interrupt Operation Procedure Instruction End Y NMI? N Y DI status? N All masked? N Y INTFNMI reset Unmasked INTFx check 2 or more Number of set flags 1 0 Other Interrupts Priority check Next Instruction Hold Highest Priority Interrupt Both interrupts of the same level are non-masked? N Y INTFx reset IE F/F reset PSW and PC saved to stack memory PC Interrupt address 62 PD78C17,78C18 3.3 MASKABLE INTERRUPT OPERATION Interrupt requests except non-maskable interrupts and the SOFTI instruction are maskable interrupts which can be enabled/disabled (IE F/F set/reset) by the EI/DI instructions and can be masked individually by means of the mask register. When an external maskable interrupt is recognized as a normal interrupt signal by an active level input for more than the specified time, an interrupt request flag is set. If an internal interrupt request is generated, an interrupt request flag is immediately set. Once the interrupt request flag is set, both the external and internal interrupts are serviced using the following procedure (see Fig. 3-3). (i) In the EI state (IE F/F = 1), a check is made to see if the interrupt request flag has been set at the end checked at end of each instruction. If the flag has been set, the interrupt cycle starts. However, interrupt requests masked by the mask register are not checked. (ii) If two or more interrupt request flags have been set simultaneously, their priorities are checked. The interrupt with the highest priority is acknowledged and the others are held pending. (iii) When an interrupt request is acknowledged, the interrupt request flag is automatically reset. If two types of interrupt requests with the same priority have both been unmasked by the mask register, the interrupt request flag is not reset. This is because the two types are identified by software at a later stage. (iv) When an interrupt request is acknowledged, the IE F/F is reset, and all interrupts except non-maskable interrupts and the SOFTI instruction are placed in the disabled state (DI state). (v) The PSW, upper PC byte, and lower PC byte are saved to the stack memory in that order. (vi) The program jumps to the interrupt address. These interrupt operations are automatically carried out in 16 states. The pending interrupt requests are acknowledged if there are no other interrupt requests of higher priority when interrupts are enabled by execution of the EI instruction. With maskable interrupts there are two types of interrupt requests with the same priority and same interrupt address. Unmasking both types, unmasking one type, or masking both kinds can be selected by setting the mask register. (1) When both types are unmasked The corresponding bits of the mask register for two types of interrupt requests are both set to "0". In this case, the interrupt request is the logical sum of the two interrupt request flags. If an interrupt request is acknowledged in accordance with the interrupt operation as a result of setting one or both interrupt request flags having the same priority and the program jumps to the interrupt address, the interrupt request flag is not reset. Therefore, the interrupt request is identified by executing a skip instruction which tests the interrupt request flag at the beginning of the interrupt service routine, and the interrupt request flag is reset. (2) When one type is unmasked For two types of interrupt requests having the same priority, the corresponding bit of the mask register for the interrupt request to be unmasked is set to "0" and the other bit is set to "1". In this case, if an interrupt request is generated by setting the unmasked interrupt request flag and that interrupt request is acknowledged in accordance with the interrupt operation, the interrupt request flag is automatically reset. When the masked interrupt request flag is set, that interrupt request is held pending. When the pending interrupt request is unmasked, it is acknowledged if there are no other interrupt requests of higher priority in the interrupt enable state. (3) When both types are masked The corresponding bits of the mask register for two types of interrupt request are both set to "1". In this case, the interrupt requests are held pending are not acknowledged when the interrupt request flag is set. When the pending interrupt requests are unmasked, they are acknowledged if there are no other interrupt requests of higher priority in the interrupt enabled state. 63 PD78C17,78C18 3.4 INTERRUPT OPERATION BY SOFTI INSTRUCTION When the SOFTI instruction is executed, the program jumps unconditionally to the interrupt address (0060H). The SOFTI instruction interrupt is not affected by the IE F/F, and the IE F/F is not affected when this instruction is executed. The servicing procedure for an interrupt generated by the SOFTI instruction is as follows: (i) The PSW, upper PC byte, and lower PC byte are saved to the stack memory in that order. (ii) The program jumps to the interrupt address (0060H). Caution If the skip condition is satisfied by the instruction (arithmetic or logical operation, increment/ decrement, shift, skip, or RETS instruction) immediately before the SOFTI instruction, the SOFTI instruction is executed and not skipped. When SOFTI instruction is executed, the SK flag of the PSW is saved as set (1) to the stack area. Thus, when the return is made from the SOFTI service routine, the PSW SK flag remains set and the instruction following the SOFTI instruction is skipped. 64 PD78C17,78C18 4. STANDBY FUNCTIONS Three standby modes are available for the PD78C17 and 78C18 to save power consumption in the program standby mode (the HALT mode, software STOP mode, and hardware STOP mode). 4.1 HALT MODE When the HLT instruction is executed, the HALT mode is set unless the interrupt request flag of the unmasked interrupt is set. In the HALT mode the CPU clock stops and program execution also stops. However, the contents of all registers and internal RAM just before the stoppage are retained. In the HALT mode, the timer, timer/event counter, serial interface, A/D converter, and interrupt control circuit are operational. Table 4-1 shows the status of the PD78C17 and 78C18 output pins in the HALT mode. Table 4-1 Output Pin Statuses Output Pin PA7 to PA0 PB7 to PB0 PC7 to PC0 PD7 to PD0 PF7 to PF0 Single ChipNote1 Data retained Data retained Data retained Data retained Data retained External Expansion Data retained Data retained Data retained High-impedance Next address retainedNote2 Data retainedNote3 High-level High-level WR, RD ALE High-level High-level Notes 1. PD78C18 only 2. Address output pin 3. Port data output pin Caution Because an interrupt request flag is used to release the HALT mode, HLT instruction execution does not set the HALT mode if even a single interrupt request flag for an unmasked interrupt is set. Thus, when setting the HALT mode when there is a possibility that an interrupt request flag may have been set (when there is a pending interrupt), one of the following procedures should be followed: First process the pending interrupt; or, reset the interrupt request flag by executing a skip instruction; or, mask all interrupts except those used to release the HALT mode. 65 PD78C17,78C18 4.2 HALT MODE RELEASE (1) Release by RESET signal When the RESET signal changes from the high to low level in the HALT mode, the HALT mode is released and the reset state is set. When the RESET signal returns to the high level, the CPU starts program execution at address 0. When the RESET signal is input, the RAM contents are retained but the contents of other registers are undefined. Fig. 4-1 HALT Mode Release Timing (RESET Signal Input) Address 0 Instruction Execution CPU HALT OSC RESET 66 PD78C17,78C18 (2) Release by interrupt request flag The HALT mode is released if at least one interrupt request flag is set by the generation of a non-maskable interrupt (NMI) or one of ten unmasked maskable interrupts (INTT0, INTT1, INT1, INT2, INTE0, INTE1, INTEIN, INTAD, INTST, and INTSR). When the HALT mode is released by a non-maskable interrupt, the instruction following the HLT instruction is not executed and the program jumps to the interrupt address (0004H) irrespective of the interrupt enabled/ disabled (EI/DI) state. When the HALT mode is released by a maskable interrupt, operation after release differs depending on whether the EI or DI state is set. (i) EI state The instruction following the HLT instruction is not executed and the program jumps to the corresponding interrupt address. Fig. 4-2 HALT Mode Release Timing (in EI State) CPU Operation HLT Interrupt Execution Interrupt Routine OSC INTFx (ii) DI state Execution restarts with the instruction following the HLT instruction (without jumping to the interrupt address). Because the interrupt request flag used for release remains set, it should be reset by a skip instruction when required. Fig. 4-3 HALT Mode Release Timing (in DI State) Following Instruction Execution CPU Operation HLT OSC INTFx 67 PD78C17,78C18 4.3 SOFTWARE STOP MODE When the STOP instruction is executed, the software STOP mode is set unless the interrupt request flag for an unmasked external interrupt is set. In the software STOP mode, all clocks stop. When this mode is set, program execution stops and the contents of all registers and internal RAM are retained (the timer upcounter is cleared to 00H). Only the NMI and RESET signals used to release the software STOP mode are valid, and all other functions stop. The statuses of the PD78C17 and 78C18 output pins in the software STOP mode are the same as for the HALT mode, as shown in Table 4-1. Cautions 1. Internal interrupts should be masked before executing the STOP instruction to prevent errors due to an internal interrupt during the oscillation stabilization time at release of the software STOP mode. The TIMER1 match signal is used as the signal to start CPU operation to secure an oscillation stabilization period after the software STOP mode has been released by setting the nonmaskable interrupt request flag. Thus, it is necessary to set a count value in TIMER REG which takes account of the oscillation stabilization time, and to set the timer mode register to the timer operating state, before executing the STOP instruction. 4.4 SOFTWARE STOP MODE RELEASE (1) Release by RESET signal When the RESET signal changes from the high to low level in the software STOP mode, the software STOP mode is released and clock oscillation starts as soon as the reset state is set. When the RESET signal is driven high after oscillation has stabilized, the CPU starts program execution at address 0. When the RESET signal changes from the high to low level, clock oscillation starts but it takes time for oscillation to stabilize. The RESET signal low-level width must therefore be longer than the oscillation stabilization time. When the RESET signal is input, the RAM contents are retained but the contents of other registers are undefined. Fig. 4-4 Software STOP Mode Release Timing (RESET Input) Address 0 Instruction Execution CPU Operation STOP 2. OSC RESET If the software STOP mode is released by the RESET signal, program execution starts at address 0 as in the case of a normal power-on reset. The SB (Standby) flag can be used to identify the program execution mode. The SB flag is set (1) when the VDD pin rises from the specified low level or below to the specified high level or above, and is reset (0) by executing a skip instruction. Thus, by testing the SB flag using a skip instruction in the program executed after RESET input, a set SB flag indicates a power-on start, and a reset SB flag indicates a start due to release of the software STOP mode. 68 PD78C17,78C18 (2) Release by interrupt request flag When the non-maskable interrupt request flag is set in the software STOP mode, the software STOP mode is released and simultaneously clock oscillation starts. When clock oscillation starts, the timer upcounter starts counting up from 00H in accordance with the setting before execution of the STOP instruction. CPU operation is started by a match signal (wait time taking account of the oscillation stabilization time) from the TIMER1 UPCOUNTER. In this case, the UPCOUNTER match signal does not set the interrupt request flag. The timer mode register of the timer after generation of the match signal is set to FFH and timer operation is stopped. After the elapse of the oscillation stabilization time, the program jumps to the interrupt address (0004H) irrespective of the interrupt enabled/disabled (EI/DI) state and without executing the instruction following the STOP instruction. FIg. 4-5 Software STOP Mode Release Timing Interrupt Execution CPU Operation STOP Interrupt Routine OSC INTFNMI Wait (Programmable) TIMER1 Match Signal 4.5 HARDWARE STOP MODE When the STOP signal changes from the high to low level, the hardware STOP mode is set. In this mode all clocks stop. When the hardware STOP mode is set, program execution stops and the internal RAM contents just before stoppage are retained, and the STOP signal used to release the hardware STOP mode is valid. All other functions stop and the reset state is set. In the hardware STOP mode, the PD78C17 and 78C18 output pins become high-impedance. 69 PD78C17,78C18 4.6 HARDWARE STOP MODE RELEASE When the STOP signal changes from the low to high level in the hardware STOP mode, the hardware STOP mode is released and simultaneously clock oscillation starts. After the elapse of the wait time (approximately 65 ms at 12 MHz) which takes account of the oscillation stabilization time, the CPU starts program execution at address 0 (see Fig. 4-6). Fig. 4-6 Hardware STOP Mode Release Timing STOP Instruction Execution CPU Operation Wait approx. 65 ms/12 MHz Address 0 Instruction Execution OSC The hardware STOP mode is not released by a high-to-low transition of the RESET signal. When the STOP signal changes from low to high while the RESET signal is low, the hardware STOP mode is released and clock oscillation starts. If the RESET signal returns from the low to high level, the CPU starts program execution at address 0 without waiting for the elapse of the oscillation stabilization time (see Fig. 4-7). For also the case where the RESET signal changes from high to low immediately after the hardware STOP mode is released (the STOP signal changes from low to high), the program is executed when the RESET signal returns from low to high (see Fig. 4-8). The oscillation stabilization time should therefore be taken into account when returning the RESET signal to the high level. After RESET signal input RAM contents are retained, but the contents of other registers are undefined. 70 PD78C17,78C18 Fig. 4-7 Hardware STOP Mode Release Timing STOP Instruction Execution CPU Operation Wait RESET Address 0 Instruction Execution OSC Fig. 4-8 Hardware STOP Mode Release Timing STOP Instruction Execution CPU Operation Wait Address 0 Instruction Execution RESET OSC In the case of a hardware STOP mode release, as with a release of the software STOP mode by means of the RESET signal, it is possible to differentiate between a power-on start and a start due to release of the hardware STOP mode by testing the SB flag using a skip instruction. 4.7 LOW SUPPLY VOLTAGE DATA RETENTION MODE The low supply voltage data retention mode can be set by decreasing the VDD supply voltage to 2.5 V after setting the software/hardware STOP mode. RAM contents can be retained with lower power consumption than in the software/hardware STOP mode. Caution The software/hardware STOP mode should not be released while in the low supply voltage data retention mode. VDD must be raised to the normal operating voltage before the release is performed. 71 PD78C17,78C18 5. RESET OPERATIONS When RESET input becomes low, then system reset is activated to create the following status. o INTERRUPT ENABLE F/F is reset and interrupt is disabled. o All the interrupt mask registers are set (1) and interrupt is masked. o An interrupt request flag is reset (0) and pended interrupt is eliminated. o All PSWs are reset (0). o 0000H is loaded into the program counter (PC). o The MODE A, MODE B, MODE C, and MODE F registers are set to FFH and the bits (MM0, 1, and 2) of the MODE CONTROL C and MEMORY MAPPING registers are respectively reset (0), then all the ports (A, B, C, D, and F) become input port (high-impedance). o All the test flags but SB flag are reset (0). o A timer mode register is set to FFH, and TIMER F/F is reset. o The mode register (ETMM, EOM) of a timer/event counter is reset (0). o The serial mode high register (SMH) of serial interface is reset (0), while the serial mode low register (SML) is set to 48H. o The A/D channel mode register of the A/D converter is reset (0). o WR, RD, ALE signals become high-impedance. o The ZC1, ZC2 bits of the zero-cross mode register (ZCM) are set (1). o Data memory and the following register contents are undefined. o The internal timing generator is initialized. Stack pointer (SP) Expansion accumulator (EA, EA'), accumulator (A, A') General register (B, C, D, E, H, L, B', C', D', E', H', L') Output latch of each port TIMER REG0, 1 (TM0, TM1) TIMER/EVENT COUNTER REG0, 1 (ETM0, ETM1) RAE bit of MEMORY MAPPING register SB flag of test flag When RESET input becomes high, the reset status is released. Then, execution of the program is started from 0000H. The contents of various kinds of registers must be initialized or re-initialized in the program, if necessary. 72 PD78C17,78C18 6. INSTRUCTION SET 6.1 IDENTIFIER/DESCRIPTION OF OPERAND Identifier r r1 r2 sr sr1 sr2 sr3 sr4 rp rp1 rp2 rp3 rpa rpa1 rpa2 rpa3 wa word byte bit f irf V, A, B, C, D, E, H, L EAH, EAL, B, C, D, E, H, L A, B, C PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, SML, EOM, ETMM, TMM, MM, MCC, MA, MB, MC, MF, TXB, TM0, TM1, ZCM PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM, RXB, CR0, CR1, CR2, CR3 PA, PB, PC, PD, PF, MKH, MKL, ANM, SMH, EOM, TMM ETM0, ETM1 ECMT, ECPT SP, B, D, H V, B, D, H, EA SP, B, D, H, EA B, D, H B, D, H, D+, H+, D-, H- B, D, H B, D, H, D+, H+, D-, H-, D+byte, H+A, H+B, H+EA, H+byte D, H, D++, H++, D+byte, H+A, H+B, H+EA, H+byte 8-bit immediate data 16-bit immediate data 8-bit immediate data 3-bit immediate data CY, HC, Z NMINote, FT0, FT1, F1, F2, FE0, FE1, FEIN, FAD, FSR, FST, ER, OV, AN4, AN5, AN6, AN7, SB Description Note NMI can also be described as FNMI. Remarks 1. sr to sr4 (special register) PA PB PC PD PF MA MB MC MCC MF MM TM0 TM1 TMM : PORT A : PORT B : PORT C : PORT D : PORT F : MODE A : MODE B : MODE C : MODE CONTROL C : MODE F : MEMORY MAPPING : TIMER REG0 : TIMER REG1 : TIMER MODE COUNTER REG0 ETM1 : TIMER/EVENT COUNTER REG1 ECNT : TIMER/EVENT COUNTER UPCOUNTER ECPT : TIMER/EVENT COUNTER CAPTURE ANM CR0 to CR3 TXB RXB SMH SML MKH MKL ZCM : TX BUFFER : RX BUFFER : SERIAL MODE High : SERIAL MODE Low : MASK High : MASK Low : ZERO CROSS MODE EOM ETMM : TIMER/EVENT COUNTER MODE : TIMER/EVENT COUNTER OUTPUT MODE : A/D CHANNEL MODE : A/D CONVERSION RESULT 0 to 3 2. rp to rp3 (register pair) SP B D H V EA : STACK POINTER : BC : DE : HL : VA : EXTENDED ACCUMULATOR 4. f (flag) CY HC Z : CARRY : HALF CARRY : ZERO 5. irf (interrupt flag) NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 to AN7 SB : STANDBY : NMI INPUT : INTFT0 : INTFT1 : INTF1 : INTF2 : INTFE0 : INTFE1 : INTFEIN : INTFAD : INTFSR : INTFST : ERROR : OVERFLOW : ANALOG INPUT 4 to 7 3. rpa to rpa3 (rp addressing) B D H D+ H+ D- H- D++ H++ D + byte H+A H+B H + EA H + byte : : : : : : : : : : : : : : (BC) (DE) (HL) (DE)+ (HL)+ (DE)- (HL)- (DE)++ (HL)++ (DE + byte) (HL + A) (HL + B) (HL + EA) (HL + byte) ETM0 : TIMER/EVENT 73 PD78C17,78C18 6.2 r R2 0 0 0 0 1 1 1 1 R1 0 0 1 1 0 0 1 1 R0 0 1 0 1 0 1 0 1 reg V A B C D E H L SYMBOL DESCRIPTION OF INSTRUCTION CODE r1 T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 0 1 0 1 0 1 reg EAH EAL B C D E H L rpa A3 A2 A1 A0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 1 0 1 0 1 addressing (BC) (DE) (HL) rpa (DE)+ (HL)+ (DE)(HL)(DE + byte) (HL + A) (HL + B) (HL + EA) (HL + byte) r2 r rpa1 rpa2 sr S5 S4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 S3 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 S2 S1 S0 0 0 0 0 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 0 0 0 1 1 0 1 0 0 1 1 0 0 1 1 0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 Special-reg PA PB PC PD PF MKH MKL ANM SMH SML EOM ETMM TMM MM MCC MA MB MC MF TXB RXB TM0 TM1 CR0 CR1 CR2 CR3 ZCM sr1 sr2 rpa3 C3 C2 C1 C0 0 0 0 0 1 1 1 1 1 0 0 1 1 0 1 1 1 1 1 1 0 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1 addressing (DE) (HL) (DE)++ (HL)++ (DE + byte) (HL + A) (HL + B) (HL + EA) (HL + byte) sr irf I4 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 rp1 I3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 I2 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 0 0 1 I1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 1 0 f Q1 0 0 1 1 0 Q0 0 1 0 1 0 reg-pair VA BC DE HL EA F2 0 0 0 1 F1 0 1 1 0 F0 0 0 1 0 flag CY HC Z I0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 INTF NMI FT0 FT1 F1 F2 FE0 FE1 FEIN FAD FSR FST ER OV AN4 AN5 AN6 AN7 SB sr3 U0 0 1 special-reg ETM0 ETM1 sr4 V0 0 1 special-reg ECNT ECPT rp P2 0 0 0 0 1 P1 0 0 1 1 0 P0 0 1 0 1 0 reg-pair SP BC DE HL EA rp Q2 0 0 0 0 1 rp2 rp3 74 PD78C17,78C18 6.3 INSTRUCTION EXECUTION TIME One state indicated in this section consists of three clock cycles. For example, one state takes 200 ns (1/15 ns x 3) at 15-MHz operation, and when executing a 4-state instruction, the minimum execution time is 0.8 s. 75 Note 1 8-bit data transfer instructions Note 2 76 Mnemonic Operand B1 r1, A A, r1 0 0 0 1 1 T2 T1 T0 0 0 0 0 1 T2 T1 T0 01001101 01001100 01110000 01110000 0 1 1 0 1 R2 R1 R0 01100100 01110001 0 1 0 0 1 0 A1 A0 01100011 00000001 A3 0 1 1 1 A2 A1 A0 A3 0 1 0 1 A2 A1 A0 00010001 00010000 01010000 00110001 rp3, EA 1 0 1 1 0 1 P1 P0 1 0 1 0 0 1 P1 P0 Instruction Code B2 B3 B4 State 4 4 r1 A A r1 sr A A sr1 r (word) (word) r r byte sr2 byte Operation Skip Condition * MOV * sr, A A, sr1 r, word word, r 1 1 S5 S4 S3 S2 S1 S0 1 1 S5 S4 S3 S2 S1 S0 0 1 1 0 1 R2 R1 R0 0 1 1 1 1 R2 R1 R0 Data S3 0 0 0 0 S2 S1 S0 Offset Data Offset Offset Data*1 Data*1 Data Data Low Adrs Low Adrs High Adrs High Adrs 10 10 17 17 7 14 13 10 10 10 7/13*3 7/13*3 4 4 4 13 (C + 1) 4 4 * MVI r, byte sr2, byte MVIW MVIX STAW LDAW STAX LDAX EXX EXA EXH BLOCK * * * * * * wa, byte rpa1, byte wa wa rpa2 rpa2 (V. wa) byte (rpa1) byte (V. wa) A A (V. wa) (rpa2) A A (rpa2) B B', C C', D D' E E', H H', L L' V, A V', A', EA EA' H, L H', L' PD78C17,78C18 (DE) + (HL) +, C C - 1 End if borrow rp3L EAL, rp3H EAH EAL rp3L, EAH rp3H DMOV EA, rp3 Notes 1. 2. Instruction Group 16-bit data transfer instructions Note 1 Mnemonic Operand B1 sr3, EA 01001000 Instruction Code B2 1 1 0 1 0 0 1 U0 1 1 0 0 0 0 0 V0 01110000 00011110 00101110 00111110 00001110 01001000 01110000 1 0 0 1 C3 C2 C1 C0 00011111 00101111 00111111 00001111 01001000 1 0 1 1 0 Q2 Q1 Q0 1 0 1 0 0 Q2 Q1 Q0 0 P2 P1 P0 0 1 0 0 01001000 Low Byte 10101000 1 1 0 0 0 R2 R1 R0 0100 1101 0101 High Byte 1 0 0 0 C3 C2 C1 C0 Data*2 Data*2 Low Adrs High Adrs Low Adrs High Adrs B3 B4 State 14 14 20 20 20 20 *3 14/20 20 20 20 20 * 14/20 13 10 10 17 8 8 8 8 3 Operation sr3 EA EA sr4 (word) C, (word + 1) B (word) E, (word + 1) D (word) L, (word + 1) H (word) SPL, (word + 1) SPH (rpa3) EAL, (rpa3 + 1) EAH C (word), B (word + 1) E (word), D (word + 1) L (word), H (word + 1) SPL (word), SPH (word + 1) EAL (rpa3), EAH (rpa3 + 1) (SP - 1) rp1H, (SP - 2) rp1L SP SP - 2 rp1L (SP), rp1H (SP + 1) SP SP + 2 rp2 word C (PC + 3 + A) B (PC + 3 + A + 1) AA+r Skip Condition DMOV EA, sr4 SBCD SDED SHLD 16-bit data transfer instructions SSPD STEAX LBCD LDED LHLD LSPD LDEAX PUSH POP LXI TABLE A, r ADD Note 2 r, A A, r ADC r, A * word word word word rpa3 word word word word rpa3 rp1 rp1 rp2, word 01100000 PD78C17,78C18 rr+A A A + r + CY r r + A + CY Notes 1. 2. Instruction Group 8-bit operation instructions (register) 77 Note 8-bit operation instructions (register) 78 Mnemonic Operand B1 A, r 01100000 Instruction Code B2 1 0 1 0 0 R2 R1 R0 0010 1110 0110 1111 0111 1011 0011 1 0 0 0 1 R2 R1 R0 0000 1001 0001 1 0 0 1 0 R2 R1 R0 0001 1 0 1 0 1 R2 R1 R0 0010 1011 0011 1110 0110 B3 B4 State 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 AA+r rr+A A A - r rr-A Operation Skip Condition No Carry No Carry ADDNC r, A A, r SUB r, A A, r SBB r, A A, r SUBNB r, A A, r ANA r, A A, r ORA r, A A, r XRA r, A A, r GTA r, A A, r LTA r, A A, r NEA r, A A A - r - CY r r - A - CY AA-r rr-A AAr rrA AAr rrA AAr rrA A-r-1 r-A-1 A-r r-A A-r r-A No Borrow No Borrow Borrow No Borrow No Borrow PD78C17,78C18 Borrow No Zero No Zero Note Instruction Group 8-bit operation instructions (register) Note Mnemonic Operand B1 A, r 01100000 Instruction Code B2 1 1 1 1 1 R2 R1 R0 0111 1100 1101 01110000 1 1 0 0 0 A2 A1 A0 1101 1010 1110 1111 1011 1 0 0 0 1 A2 A1 A0 1001 1 0 0 1 0 A2 A1 A0 1 0 1 0 1 A2 A1 A0 1011 1110 1111 1100 1101 B3 B4 State 8 8 8 8 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 A-r r-A Ar Ar Operation Skip Condition Zero Zero No Zero Zero EQA r, A ONA OFFA ADDX ADCX ADDNCX SUBX A, r A, r rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa rpa A A + (rpa) A A + (rpa) + CY A A + (rpa) A A - (rpa) A A - (rpa) - CY A A - (rpa) A A (rpa) A A (rpa) A A (rpa) A - (rpa) - 1 A - (rpa) A - (rpa) A - (rpa) A (rpa) A (rpa) No Borrow Borrow No Zero Zero No Borrow No Carry 8-bit operation instructions (memory) SBBX SUBNBX ANAX ORAX XRAX GTAX LTAX NEAX EQAX ONAX OFFAX PD78C17,78C18 No Zero Zero Note Instruction Group 79 Note Immediate data operation instructions 80 Mnemonic * ADI Operand B1 A, byte r, byte sr2, byte 01000110 01110100 0110 01010110 01110100 0110 00100110 01110100 0110 01100110 01110100 0110 01110110 01110100 0110 00110110 01110100 0110 00000111 01110100 Instruction Code B2 Data 0 1 0 0 0 R2 R1 R0 S3 1 0 0 0 S2 S1 S0 Data 0 1 0 1 0 R2 R1 R0 S3 1 0 1 0 S2 S1 S0 Data 0 0 1 0 0 R2 R1 R0 S3 0 1 0 0 S2 S1 S0 Data 0 1 1 0 0 R2 R1 R0 S3 1 1 0 0 S2 S1 S0 Data 0 1 1 1 0 R2 R1 R0 S3 1 1 1 0 S2 S1 S0 Data 0 0 1 1 0 R2 R1 R0 S3 0 1 1 0 S2 S1 S0 Data 0 0 0 0 1 R2 R1 R0 Data Data Data Data Data Data Data B3 B4 State 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 20 7 11 Operation A A + byte r r + byte sr2 sr2 + byte A A + byte + CY r r + byte + CY sr2 sr2 + byte + CY A A + byte r r + byte sr2 sr2 + byte A A - byte r r - byte sr2 sr2 - byte A A - byte - CY r r - byte - CY sr2 sr2 - byte - CY A A - byte r r - byte sr2 sr2 - byte A A byte r r byte Skip Condition * ACI A, byte r, byte sr2, byte * ADINC A, byte r, byte sr2, byte No Carry No Carry No Carry * SUI A, byte r, byte sr2, byte * SBI A, byte r, byte sr2, byte * SUINB A, byte r, byte sr2, byte No Borrow No Borrow PD78C17,78C18 No Borrow * ANI A, byte r, byte Note Instruction Group Note Mnemonic ANI * ORI Operand B1 sr2, byte A, byte r, byte sr2, byte 01100100 00010111 01110100 0110 00010110 01110100 0110 00100111 01110100 0110 00110111 01110100 0110 01100111 01110100 0110 01110111 01110100 0110 Instruction Code B2 S3 0 0 0 1 S2 S1 S0 Data 0 0 0 1 1 R2 R1 R0 S3 0 0 1 1 S2 S1 S0 Data 0 0 0 1 0 R2 R1 R0 S3 0 0 1 0 S2 S1 S0 Data 0 0 1 0 1 R2 R1 R0 S3 0 1 0 1 S2 S1 S0 Data 0 0 1 1 1 R2 R1 R0 S3 0 1 1 1 S2 S1 S0 Data 0 1 1 0 1 R2 R1 R0 S3 1 1 0 1 S2 S1 S0 Data 0 1 1 1 1 R2 R1 R0 S3 1 1 1 1 S2 S1 S0 Data Data Data Data Data Data B3 Data B4 State 20 7 11 20 7 11 20 7 11 14 7 11 14 7 11 14 7 11 14 Operation sr2 sr2 byte A A byte r r byte sr2 sr2 byte A A byte r r byte sr2 sr2 byte A - byte- 1 r - byte - 1 sr2 - byte - 1 A - byte r - byte sr2 - byte A - byte r - byte sr2 - byte A - byte r - byte sr2 - byte Skip Condition * XRI Immediate data operation instructions A, byte r, byte sr2, byte * GTI A, byte r, byte sr2, byte No Borrow No Borrow No Borrow Borrow Borrow Borrow No Zero No Zero No Zero Zero * LTI A, byte r, byte sr2, byte * NEI A, byte r, byte sr2, byte * EQI A, byte r, byte sr2, byte PD78C17,78C18 Zero Zero Note Instruction Group 81 Note Immediate data operation instructions Working register operation instructions 82 Mnemonic * ONI Operand B1 A, byte r, byte sr2, byte 01000111 01110100 0110 01010111 01110100 0110 01110100 Instruction Code B2 Data 0 1 0 0 1 R2 R1 R0 S3 1 0 0 1 S2 S1 S0 Data 0 1 0 1 1 R2 R1 R0 S3 1 0 1 1 S2 S1 S0 11000000 1101 1010 1110 1111 1011 10001000 1001 10010000 10101000 1011 1110 1111 1100 offset Data Data B3 B4 State 7 11 14 7 11 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 A byte r byte sr2 byte A byte r byte sr2 byte Operation Skip Condition No Zero No Zero No Zero Zero Zero Zero * OFFI A, byte r, byte sr2, byte ADDW ADCW ADDNCW SUBW SBBW SUBNBW ANAW ORAW XRAW GTAW LTAW NEAW EQAW ONAW wa wa wa wa wa wa wa wa wa wa wa wa wa wa A A + (V. wa) A A + (V. wa) + CY A A + (V. wa) A A - (V. wa) A A - (V. wa) - CY A A - (V. wa) A A (V. wa) A A (V. wa) A A (V. wa) A - (V. wa) - 1 A - (V. wa) A - (V. wa) A - (V. wa) A (V. wa) No Borrow Borrow No Borrow No Carry PD78C17,78C18 No Zero Zero No Zero Note Instruction Group Note Mnemonic OFFAW wa * * * * * * * * Operand B1 01110100 00000101 0001 0010 0011 0110 0111 0100 0101 01110000 0100 Instruction Code B2 11011000 Offset B3 Offset Data B4 State 14 19 19 13 13 13 13 13 13 A (V. wa) Operation Skip Condition Zero Working register operation instructions ANIW ORIW GTIW LTIW NEIW EQIW ONIW OFFIW EADD DADD DADC wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte wa, byte EA, r2 EA, rp3 EA, rp3 EA, rp3 EA, r2 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 (V. wa) (V. wa) byte (V. wa) (V. wa) byte (V. wa) - byte - 1 (V. wa) - byte (V. wa) - byte (V. wa) - byte (V. wa) byte (V. wa) byte EA EA + r2 EA EA + rp3 EA EA + rp3 +CY EA EA + rp3 EA EA - r2 EA EA - rp3 EA EA - rp3 - CY EA EA - rp3 EA EA rp3 EA EA rp3 EA EA rp3 No Borrow No Carry No Borrow Borrow No Zero Zero No Zero Zero 0 1 0 0 0 0 R1 R0 1 1 0 0 0 1 P1 P0 1101 1010 11 11 11 11 11 11 11 11 11 11 11 16-bit operation instructions DADDNC ESUB DSUB DSBB DSUBNB DAN DOR DXR 0000 0100 0 1 1 0 0 0 R1 R0 1 1 1 0 0 1 P1 P0 1111 1011 1 0 0 0 1 1 P1 P0 1001 1 0 0 1 0 1 P1 P0 PD78C17,78C18 Note Instruction Group 83 Note 1 16-bit operation instructions Note 2 Addition/subtraction instructions Note 3 84 Mnemonic DGT DLT DNE DEQ DON DOFF MUL DIV INR INRW * Operand B1 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 EA, rp3 r2 r2 r2 wa rp 0 1 0 0 0 0 R1 R0 00100000 0 0 P1 P0 0 0 1 0 10101000 0 1 0 1 0 0 R1 R0 00110000 0 0 P1 P0 0 0 1 1 10101001 01100001 01001000 01001000 01110100 Instruction Code B2 1 0 1 0 1 1 P1 P0 1011 1110 1111 1100 1101 0 0 1 0 1 1 R1 R0 0011 B3 B4 State 11 11 11 11 11 11 32 59 4 EA - rp3 - 1 EA - rp3 EA - rp3 EA - rp3 EA rp3 EA rp3 EA A x r2 Operation Skip Condition No Borrow Borrow No Zero Zero No Zero Zero EA EA / r2, r2 Remainder r2 r2 + 1 (V. wa) (V. wa) + 1 rp rp + 1 EA EA + 1 r2 r2 - 1 (V. wa) (V. wa) - 1 rp rp - 1 EA EA - 1 Decimal Adjust Accumulator Borrow Borrow Carry Carry Offset 16 7 7 4 INX EA DCR DCRW * r2 wa rp DCX EA DAA STC CLC NEGA 7 4 00101011 00101010 00111010 8 8 8 Offset 16 7 PD78C17,78C18 CY 1 CY 0 AA+1 Note 1. 2. 3. Instruction Group Multiply/divide instructions Other operation instructions Note Mnemonic RLD RRD RLL RLR r2 r2 r2 r2 r2 r2 EA EA EA EA * Operand B1 01001000 Instruction Code B2 00111000 1001 0 1 R1 R0 0 0 R1 R0 0 0 1 0 0 1 R1 R0 0 0 R1 R0 0 0 0 0 0 1 R1 R0 0 0 R1 R0 10110100 0000 10100100 0000 01010100 00100001 Low Adrs High Adrs B3 B4 State 17 17 8 8 8 8 8 8 8 8 8 8 10 4 10 Operation Rotate Left Digit Rotate Right Digit r2m + 1 r2m, r20 CY, CY r27 r2m - 1 r2m, r27 CY, CY r20 r2m + 1 r2m, r20 0, CY r27 r2m - 1 r2m, r27 0, CY r20 r2m + 1 r2m, r20 0, CY r27 r2m - 1 r2m, r27 0, CY r20 EAn + 1 EAn, EA0 CY, CY EA15 EAn - 1 EAn, EA15 CY, CY EA0 EAn + 1 EAn, EA0 0, CY EA15 EAn - 1 EAn, EA15 0, CY EA0 PC word PCH B, PCL C PC PC + 1 + jdisp 1 PC PC + 2 + jdisp PC EA Skip Condition Rotation/shift instructions SLL SLR SLLC SLRC DRLL DRLR DSLL DSLR JMP Carry Carry word Jump instructions JB JR JRE JEA * word word 11 jdisp 1 jdisp 00101000 Low Adrs 00101001 fa High Adrs 0100111 01001000 10 8 16 17 13 PD78C17,78C18 CALL CALB CALF * word 01000000 01001000 * word 01111 (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L PC word, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L PCH B, PCL C, SP SP - 2 (SP - 1) (PC + 2)H, (SP - 2) (PC + 2)L PC15 - 11 00001, PC10 - 0 fa, SP SP - 2 Call Instructions Note Instruction Group 85 Note 1 Note 2 Return instructions Skip instructions CPU control instructions 86 Mnemonic CALT SOFTI RET RETS RETI BIT SK SKN SKIT SKNIT NOP EI DI HLT STOP * Operand B1 word 100 ta Instruction Code B2 B3 B4 State 16 16 10 10 13 Operation (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L PCL (128 + 2ta), PCH (129 + 2ta), SP SP - 2 (SP - 1) PSW, (SP - 2) (PC + 1)H, (SP - 3) (PC + 1)L, PC 0060H, SP SP - 3 PCL (SP), PCH (SP + 1) SP SP + 2 PCL (SP), PCH (SP + 1), SP SP + 2 PC PC + n PCL (SP), PCH (SP + 1) PSW (SP + 2), SP SP + 3 Skip if (V. wa) bit = 1 Skip if f = 1 Skip if f = 0 Skip if irf = 1, then reset irf Skip if irf = 0 Reset irf, if irf = 1 No Operation Enable Interrupt Disable Interrupt Set Halt Mode Set Stop Mode Skip Condition 01110010 10111000 1001 01100010 bit, wa f f irf irf 00000000 10101010 10111010 01001000 01001000 00111011 10111011 0 1 0 1 1 B2 B1 B0 01001000 Offset 0 0 0 0 1 F2 F1 F0 0001 0 1 0 I4 I3 I2 I1 I0 0 1 1 I4 I3 I2 I1 I0 Unconditional skip 10 8 8 8 8 4 4 4 12 12 (V. wa)bit =1 f=1 f=0 irf = 1 irf = 0 * 1. Data is B2 if rpa2 = 2. Data is B3 if rpa3 = 3. In the State item, a Remarks The idle state D + byte, H + byte. D + byte, H + byte. figure is in the right side of slash if rpa2 and rpa3 are D + byte, H + A, H + B, H + EA, H + byte. when each instruction is skipped is different from the execution state as shown below. : : : 4 states 7 states 8 states 3-byte instruction (with *) : 3-byte instruction : 4-byte instruction : 10 states 11 states 14 states PD78C17,78C18 Notes 1-byte instruction 2-byte instruction (with *) 2-byte instruction 1. Instruction Group 2. Call instructions PD78C17,78C18 7. LIST OF MODE REGISTERS Name of Mode Registers MA MB MCC MODE A register MODE B register MODE CONTROL C register MODE C register MEMORY MAPPING register MODE F register Timer mode register Timer/event counter mode register Timer/event counter output mode register Read/ Write W W W Function Specifies bit-wise the input/output of the port A. Specifies bit-wise the input/output of the port B. Specifies bit-wise the port/control mode of the port C. MC MM W W Specifies bit-wise the input/output of the port C which is in port mode. Specifies the port/expansion mode of port D and port F. MF TMM ETMM W R/W W Specifies bit-wise the input/output of the port F which is in port mode. Specifies operating mode of timer. Specifies the operating mode of timer/event counter. EOM R/W Control the output level of CO0 and CO1. SML Serial mode register SMH MKL Interrupt mask register MKH ANM A/D channel mode register Zero-cross mode register W Specifies the operating mode of serial interface. R/W R/W Specifies the enable/disable of the interrupt request. 5 R/W Specifies the operating mode of A/D converter. ZCM W Specifies the operation of zero-cross detector circuit. 87 PD78C17,78C18 8. ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (TA = 25 C) PARAMETER Power supply voltage SYMBOL VDD AVDD AVSS TEST CONDITIONS RATINGS -0.5 to +7.0 AVSS to VDD + 0.5 -0.5 to +0.5 -0.5 to VDD + 0.5 -0.5 to VDD + 0.5 UNIT V V V V V mA mA mA mA V C C Input voltage Output voltage Output current, low VI VO IOL Per pin Total of all output pins 4.0 100 -2.0 -50 -0.5 to AVDD + 0.3 Output current, high IOH Per pin Total of all output pins A/D converter reference input voltage VAREF 5 Operating ambient temperature Storage temperature TA -40 to +85 Tstg -65 to +150 5 Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. The absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product with these rated values never exceeded. 88 PD78C17,78C18 OSCILLATOR CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V, VDD - 0.8 V AVDD VDD, 3.4 V VAREF AVDD) RESONATOR Ceramic or crystal resonator RECOMMENDED CIRCUIT PARAMETER Oscillation frequency (fXX) TEST CONDITIONS A/D converter not used MIN. 4 MAX. 15 UNIT MHz X1 X2 C1 C2 A/D converter used 5.8 15 MHz External clock X1 X2 X1 input frequency (fX) A/D converter not used A/D converter used 4 15 MHz 5.8 15 MHz X1 rise time, fall time (tr, tf) HCMOS Inverter 0 20 ns X1 input high, low level width (tOH, tOL) 20 250 ns Cautions 1. 2. Place the oscillator as close as possible to X1, X2 pins. Ensure that no other signal lines are routed through the area enclosed with dotted lines. CAPACITANCE (TA = 25 C, VDD = VSS = 0 V) PARAMETER Input capacitance Output capacitance Input-output capacitance SYMBOL CI CO CIO TEST CONDITIONS fC = 1 MHz Unmeasured pins returned to 0 V MIN. TYP. MAX. 10 20 20 UNIT pF pF pF 89 PD78C17,78C18 DC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V) PARAMETER Input voltage, low SYMBOL VIL1 TEST CONDITIONS All except RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4 RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4 All except RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4, X1, X2 RESET, STOP, NMI, SCK, INT1, TI, AN7 to AN4, X1, X2 IOL = 2.0 mA IOH = -1.0 mA IOH = -100 A INT1Note1, TI (PC3)Note2 ; 0 V VI VDD All except INT1, TI (PC3); 0 V VI VDD 0 V VO VDD MIN. 0 TYP. MAX. 0.8 UNIT V VIL2 0 0.2VDD V Input voltage, high VIH1 2.2 VDD V VIH2 0.8VDD VDD V Output voltage, low Output voltage, high VOL VOH 0.45 VDD - 1.0 VDD - 0.5 200 10 10 V V V Input current Input leakage current Output leakage current AVDD power supply current II ILI A A A ILO AIDD1 AIDD2 Operating mode fXX = 15 MHz STOP mode Operating mode fXX = 15 MHz HALT mode fXX = 15 MHz Hardware/software STOP mode 2.5 0.5 10 16 7 1.3 20 30 13 mA A mA mA V VDD power supply current IDD1 IDD2 Data retention voltage Data retention current VDDDR IDDDR Hardware/softwareNote3 STOP mode VDDDR = 2.5 V VDDDR = 5 V 10 % 3.5 V VDD 5.5 V, VI = 0 V 17 1 10 27 15 50 75 A A k Pull-up resistor RL Ports A, B, and C Notes 1. If self-bias should be generated by ZCM register. 2. If the control mode is set by MCC register, and self-bias should be generated by ZCM register. 3. If self-bias is not generated. 90 PD78C17,78C18 AC CHARACTERISTICS (TA = -40 to +85 C, VDD = AVDD = +5.0 V 10 %, VSS = AVSS = 0 V) Read/write Operation: PARAMETER X1 input cycle time Address setup time (to ALE ) Address hold time (from ALE ) RD delay time from address Address float time from RD Data input time from address Data input time from ALE Data input time from RD RD delay time from ALE Data hold time (from RD ) ALE delay time from RD RD low-level width SYMBOL tCYC tAL tLA tAR tAFR tAD tLDR tRD tLR tRDH tRL tRR CL = 100 pF fXX = 15 MHz, CL = 100 pF In Data Read fXX = 15 MHz, CL = 100 pF In OP Code Fetch fXX = 15 MHz, CL = 100 pF ALE high-level width M1 setup time (to ALE ) M1 hold time (from ALE ) IO/M setup time (to ALE ) IO/M hold time (from ALE ) WR delay time from address Data output time from ALE Data output time from WR WR delay time from ALE Data setup time (to WR ) Data hold time (from WR ) ALE delay time from WR WR low-level width tLL tML tLM tIL tLI tAW tLDW tWD tLW tDW tWDH tWL tWW CL = 100 pF fXX = 15 MHz, CL = 100 pF 15 165 60 80 215 fXX = 15 MHz, CL = 100 pF fXX = 15 MHz, CL = 100 pF fXX = 15 MHz 15 0 80 215 CL = 100 pF fXX = 15 MHz, CL = 100 pF fXX = 15 MHz, CL = 100 pF TEST CONDITIONS MIN. 66 30 35 100 20 250 135 120 MAX. 250 UNIT ns ns ns ns ns ns ns ns ns ns ns ns 415 ns 90 30 35 30 35 100 180 100 ns ns ns ns ns ns ns ns ns ns ns ns ns 91 PD78C17,78C18 Serial Operation : PARAMETER SCK cycle time SYMBOL tCYK SCK input TEST CONDITIONS Note1 Note2 SCK output SCK low-level width tKKL SCK input Note1 Note2 SCK output SCK high-level width tKKH SCK input Note1 Note2 SCK output RXD setup time (to SCK ) RXD hold time (from SCK ) TXD delay time from SCK tRXK tKRX tKTX Note1 Note1 Note1 MIN. 800 400 1.6 335 160 700 335 160 700 80 80 210 MAX. UNIT ns ns s ns ns ns ns ns ns ns ns ns Notes 1. If clock rate is x1 in asynchronous mode, synchronous mode, or I/O interface mode. 2. If clock rate is x16 or x64 in asynchronous mode. Remark The numeric values in the table are those when fXX = 15 MHz, CL = 100 pF. Zero-Cross Characteristics : PARAMETER Zero-cross detection input Zero-cross accuracy Zero-cross detection input frequency SYMBOL VZX AZX fZX 0.05 TEST CONDITIONS AC combination 60-Hz sine wave MIN. 1 MAX. 1.8 135 1 UNIT VACP-P mV kHz Other Operation : PARAMETER TI high, low-level width CI high, low-level width SYMBOL tTIH, tTIL tCI1H, tCI1L tCI2H,tCI2L NMI high, low-level width INT1 high, low-level width INT2 high, low-level width AN7 to AN4, low-level width RESET high, low-level width tNIH, tNIL tI1H, tI1L tI2H, tI2L tANH, tANL tRSH, tRSL Event count mode Pulse width test mode TEST CONDITIONS MIN. 6 6 48 10 36 36 36 10 MAX. UNIT tCYC tCYC tCYC s tCYC tCYC tCYC s 92 PD78C17,78C18 A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 C, VDD = +5.0 V 10 %, VSS = AVSS = 0 V, VDD - 0.5 V AVDD VDD, 3.4 V VAREF AVDD) PARAMETER Resolution Absolute accuracyNote SYMBOL TEST CONDITIONS MIN. 8 TYP. MAX. UNIT Bits 3.4 V VAREF AVDD, 66 ns tCYC 170 ns 4.0 V VAREF AVDD, 66 ns tCYC 170 ns TA = -10 to +70 C, 4.0 V VAREF AVDD, 66 ns tCYC 170 ns 0.8 % 0.6 % 0.4 % FSR FSR FSR Conversion time tCONV 66 ns tCYC 110 ns 110 ns tCYC 170 ns 576 432 96 72 -0.3 50 VAREF + 0.3 tCYC tCYC tCYC tCYC V M Sampling time tSAMP 66 ns tCYC 110 ns 110 ns tCYC 170 ns Analog input voltage Analog input impedance Reference voltage VAREF current VIAN RAN AN7 to AN0 (including unused pins) 5 VAREF IAREF1 IAREF2 Operating mode STOP mode Operating mode fXX = 15 MHz STOP mode 3.4 1.5 0.7 0.5 10 AVDD 3.0 1.5 1.3 20 V mA mA mA AVDD power supply current AIDD1 AIDD2 A Note Quantization error (1/2 LSB) is not included. AC Timing Test Point VDD - 1.0 V 0.45 V 2.2 V 0.8 V Test Points 2.2 V 0.8 V 93 PD78C17,78C18 tCYC-Dependent AC Characteristics Expression PARAMETER tAL tLA tAR tAD tLDR tRD tLR tRL tRR 2T - 100 T - 30 3T - 100 7T - 220 5T - 200 4T - 150 T - 50 2T - 50 4T - 50 (In data read) 7T - 50 (In OP code fetch) tLL tML tLM tIL tLI tAW tLDW tLW tDW tWDH tWL tWW tCYK 2T - 40 2T - 100 T - 30 2T - 100 T - 30 3T - 100 T + 110 T - 50 4T - 100 2T - 70 2T - 50 4T - 50 6T (SCK input)Note1/12T (SCK input)Note2 24T (SCK output) tKKL 2.5T + 5 (SCK input)Note1/5T + 5 (SCK input)Note2 12T - 100 (SCK output) tKKH 2.5T + 5 (SCK input)Note1/5T + 5 (SCK input)Note2 12T - 100 (SCK output) MIN. ns MIN. ns MIN. MIN. MIN. MIN. MIN. MIN. MAX. MIN. MIN. MIN. MIN. MIN. MIN. ns ns ns ns ns ns ns ns ns ns ns ns ns EXPRESSION MIN./MAX. MIN. MIN. MIN. MAX. MAX. MAX. MIN. MIN. MIN. UNIT ns ns ns ns ns ns ns ns ns Notes 1. If clock rate is x16, x64 in asynchronous mode. 2. If clock rate is x1, in asynchronous mode, synchronous mode, or I/O interface mode. Remarks 1. T = tCYC = 1/fXX 2. Other items which are not listed in this table are not dependent on oscillator frequency (fXX). 94 PD78C17,78C18 TIMING WAVEFORM Read Operation tCYC X1 PF7 to PF0 tAD PD7 to PD0 Address (Lower) tLL ALE tAL RD tLR tAR tML MODE1 (M1)Note1 MODE0 (IO/M)Note2 tLM tLA tAFR tLDR Address (Upper) Read Data tRDH tRL tRD tRR tIL tLI Notes 1. When MODE1 pin is pulled up, M1 signal is output to MODE1 pin in the 1st OP code fetch cycle. 2. When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register read cycle. Write Operation X1 PF7 to PF0 tLDW PD7 to PD0 Address (Lower) tLL ALE tAL WR tLW tAW tIL MODE0 (IO/M) Note tLI tLA tWD Address (Upper) Write Data tDW tWDH tWW tWL Note When MODE0 pin is pulled up, IO/M signal is output to MODE0 pin in sr to sr2 register write cycle. 95 PD78C17,78C18 Serial Operation tCYK tKKL SCK tKTX TXD tKKH RXD tRXK tKRX Timer Input Timing tTIH tTIL TI Timer/event Counter Input Timing Event Counter Mode tCI1H tCI1L CI Pulse Width Test Mode tCI2H tCI2L CI 96 PD78C17,78C18 Interrupt Input Timing tNIH tNIL NMI tI1L tI1H INT1 tI2H tI2L INT2 Reset Input Timing tRSH tRSL RESET 0.8VDD 0.2VDD External Clock Timing tH 0.8VDD X1 0.8 V tr tCYC tf tL 97 PD78C17,78C18 DATA MEMORY STOP MODE LOW POWER SUPPLY VOLTAGE DATA RETENTION (TA = -40 to +85 C) PARAMETER Data retention power supply voltage Data retention power supply current SYMBOL VDDDR TEST CONDITIONS MIN. 2.5 TYP. MAX. 5.5 UNIT V IDDDR VDDDR = 2.5 V VDDDR = 5 V 10 % 1 10 200 12T + 0.5 15 50 A A s s s 5 VDD rise/fall time STOP setup time (to VDD) STOP hold time (from VDD) tRVD, tFVD tSSTVD tHVDST 12T + 0.5 Data Retention Timing 90 % VDD 10 % tFVD tSSTVD STOP VDDDR tRVD tHVDST VIH2 VIL2 98 PD78C17,78C18 9. CHARACTERISTIC CURVES IDD1, IDD2 vs VDD 30 (TA = 25 C, fXX = 15 MHz) 25 IDD1 (TYP.) VDD Power Supply Current IDD1, IDD2 [mA] 20 15 10 IDD2 (TYP.) 5 0 0 4.5 5.0 Power Supply Voltage VDD [V] 5.5 IDD1, IDD2 vs fXX 30 (TA = 25 C, VDD = 5 V) VDD Power Supply Current IDD1, IDD2 [mA] IDD1 (TYP.) 20 10 IDD2 (TYP.) 0 0 5 10 15 Oscillation Frequency fXX [MHz] 99 PD78C17,78C18 IOL vs VOL (TA = 25 C, VDD = 5 V) 2.5 TYP. 2.0 Output Current Low IOL [mA] 1.5 1.0 0.5 0 0 0.1 0.2 0.3 0.4 0.5 Output Voltage Low VOL [V] IOH vs VOH (TA = 25 C, VDD = 5 V) -1.5 TYP. Output Current High IOH [mA] -1.0 -0.5 0 0 0.1 0.2 0.3 0.4 0.5 Power Supply Voltage - Output Voltage High VDD - VOH [V] 100 PD78C17,78C18 IDDDR vs VDDDR (TA = 25 C) 10 Data Retention Power Supply Current IDDDR [A] 8 6 4 TYP. 2 0 0 2 3 4 5 6 Data Retention Power Supply Voltage VDDDR [V] 101 PD78C17,78C18 10. PACKAGE DRAWINGS 64 PIN PLASTIC SHRINK DIP (750 mil) 64 33 1 A 32 K L J I F D G H N M C B M R NOTE 1) Each lead centerline is located within 0.17 mm (0.007 inch) of its true position (T.P.) at maximum material condition. 2) Item "K" to center of leads when formed parallel. ITEM A B C D F G H I J K L M N R MILLIMETERS 58.68 MAX. 1.78 MAX. 1.778 (T.P.) 0.500.10 0.9 MIN. 3.20.3 0.51 MIN. 4.31 MAX. 5.08 MAX. 19.05 (T.P.) 17.0 0.25 +0.10 -0.05 0.17 0~15 INCHES 2.311 MAX. 0.070 MAX. 0.070 (T.P.) 0.020 +0.004 -0.005 0.035 MIN. 0.1260.012 0.020 MIN. 0.170 MAX. 0.200 MAX. 0.750 (T.P.) 0.669 0.010 +0.004 -0.003 0.007 0~15 P64C-70-750A,C-1 102 PD78C17,78C18 64 PIN PLASTIC QFP (14x20) A B 51 52 33 32 detail of lead end C D S 64 1 20 19 F G H IM J K P N L P64GF-100-3B8,3BE,3BR-1 NOTE Each lead centerline is located within 0.20 mm (0.008 inch) of its true position (T.P.) at maximum material condition. ITEM A B C D F G H I J K L M N P Q S MILLIMETERS 23.6 0.4 20.0 0.2 14.0 0.2 17.6 0.4 1.0 1.0 0.40 0.10 0.20 1.0 (T.P.) 1.8 0.2 0.8 0.2 0.15+0.10 -0.05 0.12 2.7 0.1 0.1 3.0 MAX. INCHES 0.929 0.016 0.795+0.009 -0.008 0.551+0.009 -0.008 0.693 0.016 0.039 0.039 0.016 +0.004 -0.005 0.008 0.039 (T.P.) 0.071-0.009 0.031+0.009 -0.008 0.006+0.004 -0.003 0.005 0.106 0.004 0.004 0.119 MAX. +0.008 M 55 Q 103 PD78C17,78C18 64 PIN PLASTIC QUIP (UNIT: mm) A 64 33 1 32 W X P S M H I M J K N C P64GQ-100-36 NOTE Each lead centerline is located within 0.25 mm (0.010 inch) of its true position (T.P.) at maximum material condition. ITEM A C H I J K M N P S W X MILLIMETERS 41.5 16.5 - 0.50 +0.10 +0.3 -0.2 INCHES 1.634+0.012 -0.008 0.650 0.020 +0.004 -0.005 0.010 0.100 (T.P.) 0.050 (T.P.) 0.043+0.011 -0.006 0.010 +0.004 -0.003 0.157+0.013 -0.012 0.142-0.005 0.950 - +0.042 +0.042 +0.004 0.25 2.54 (T.P.) 1.27 (T.P.) 1.1 +0.25 -0.15 +0.10 0.25 -0.05 +0.3 4.0 - 3.6 - +0.1 - 24.13 +1.05 - 19.05 +1.05 0.750 - 104 PD78C17,78C18 11. RECOMMENDED SOLDERING CONDITIONS This PD78C17 and 78C18 should be soldered and mounted under the following recommended conditions. For details of the conditions, refer to the document "Surface Device Mounting Technology Manual" (IEI1207). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 11-1 Surface Mounting Type Soldering Conditions 5 PD78C17GF-3BE: 64-pin plastic QFP (14 x 20 mm) PD78C18GF-xxx-3BE: 64-pin plastic QFP (14 x 20 mm) Soldering Method Infrared ray reflow Soldering Conditions Package peak temperature: 235 C, Time: Within 30 s (at 210 C or higher), Count: Twice or less VSP VP15-00-2 Wave soldering WS60-00-1 Partial heating -- Caution Do not use several soldering methods in combination (except partial heating). Table 11-2 Through-Hole Type Soldering Condition PD78C17CW: PD78C18CW-xxx: PD78C17GQ-36: PD78C18GQ-xxx-36: 64-pin plastic shrink DIP (750 mils) 64-pin plastic shrink DIP (750 mils) 64-pin plastic QUIP 64-pin plastic QUIP Soldering Conditions Solder bath temperature: 260 C or lower, Time: Within 10 s Pin temperature: 300 C or lower, Time: Within 3 s (per pin) Soldering Method Wave soldering (pin only) Partial heating Caution Wave soldering must be applied to pins only, and care must be taken to prevent solder from coming into direct with the package body. 105 PD78C17,78C18 12. DIFFERENCES AMONG PD78C18, PD78C14, AND PD78C12A Part Number Item Internal ROM Internal RAM Port A to Port C PD78C18 32 K x 8 1Kx8 On-chip pull-up resistor selectable bit-wise by mask option * 64-pin plastic shrink DIP (750 mil) * 64-pin plastic QFP (14 x 20 mm) * 64-pin plastic QUIP PD78C14 16 K x 8 256 x 8 No on-chip pull-up resistor PD78C12A 8Kx8 On-chip pull-up resistor selectable bit-wise by mask option * 64-pin plastic (750 mil) * 64-pin plastic (14 x 20 mm) * 64-pin plastic * 64-pin plastic (straight) * 68-pin plastic shrink DIP QFP QUIP QUIP QFJ Package * 64-pin plastic (750 mil) * 64-pin plastic (14 x 20 mm) * 64-pin plastic * 64-pin plastic (straight) shrink DIP QFP QUIP QUIP 106 PD78C17,78C18 APPENDIX DEVELOPMENT TOOLS The following development tools are available to develop a system which uses the PD78C17 or 78C18. Language Processor 87AD series relocatable assembler (RA87) This is a program which converts a program written in mnemonic to an object code for which microcontroller execution is possible. Besides, it contains a function to automatically create a symbol table, and optimize a branch instruction. 5 Host Machine PC-9800 series OS MS-DOSTM Ver. 2.11 to Ver. 5.00ANote PC DOSTM (Ver. 3.1) Supply Medium 3.5-inch 2HD Ordering Code (Product Name) S5A13RA87 5-inch 2HD 3.5-inch 2HC 5-inch 2HC S5A10RA87 S7B13RA87 S7B10RA87 IBM PC/ATTM PROM Write Tools PG-1500 With a provided board and an optional programmer adapter connected, this PROM programmer can manipulate from a stand-alone or host machine to perform programming on single-chip microcontroller which incorporates PROM. It is also capable of programming a typical PROM ranging from 256 K to 4 Mbits. PROM programmer adapter for the PD78CP18. Used by connecting to PG-1500. Hardware PA-78CP14CW/ GF/GQ PA-78CP14CW PA-78CP14GF PA-78CP14GQ PG-1500 controller For the PD78CP18CW For the PD78CP18GF-3BE For the PD78CP18GQ-36 Connected PG-1500 to a host machine by using serial and parallel interfaces, to control the PG1500 on a host machine. Host Machine OS MS-DOS Ver. 2.11 to Ver. 5.00ANote PC DOS (Ver. 3.1) Ordering Code (Product Name) Supply Medium 3.5-inch 2HD Software PC-9800 series S5A13PG1500 5-inch 2HD 5-inch 2HC S5A10PG1500 S7B10PG1500 IBM PC/AT Note Remark Ver. 5.00/5.00A are provided with the task swap function, but it cannot be used with this software. Operation of assemblers and the PG-1500 controller are guaranteed only on the host machines and operating systems shown above. 107 PD78C17,78C18 Debugging tools An in-circuit emulator (IE-78C11-M) is available as a program debugging tool for the PD78C17 and 78C18. The following table shows its system configuration. Hardware IE-78C11-M The IE-78C11-M is an in-circuit emulator which works with 87AD series. It can be connected to a host machine to perform efficient debugging. Connects the IE-78C11-M to host machine by using the RS-232C, then controls the IE-78C11-M on host machine. IE-78C11-M control program (IE controller) Host Machine Software PC-9800 series OS MS-DOS Ver. 2.11 to Ver. 3.30D PC DOS (Ver. 3.1) Supply Medium 3.5-inch 2HD Ordering Code (Product Name) S5A13IE78C11 S5A10IE78C11 S7B10IE78C11 5-inch 2HD IBM PC/AT 5-inch 2HC Remark Operation of the IE controller is guaranteed only on the host machine and operating systems quoted above. 108 PD78C17,78C18 NOTES FOR CMOS DEVICES 1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be Semiconductor adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function. MS-DOS is a trademark of Microsoft Corporation. PC/AT and PC DOS are trademarks of IBM Corporation. 109 PD78C17,78C18 The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative. License not needed: PD78C17CW, 78C17GF-3BE, and 78C17GQ-36 The customer must judge the need for license: PD78C18CW-xxx, 78C18GF-xxx-3BE, and 78C18GQ-xxx-36 No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customer must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices in "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact NEC Sales Representative in advance. Anti-radioactive design is not implemented in this product. M4 94.11 |
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